16Gb: 2 Channels x16/x8 GDDR6 SGRAM Features GDDR6 SGRAM MT61K512M32 2 Channels x 512 Meg x 16 I/O, 2 Channels x 1 Gig x 8 I/O Low power modes Features Onchip temperature sensor with readout V = V = 1.35V 3% and 1.25V 3% DD DDQ Auto precharge option for each burst access V = 1.8V 3%/+6% PP Auto refresh mode (32ms, 16k cycles) with per-bank Data rate: 14 Gb/s, 16 Gb/s and per-2-bank refresh options 2 separate independent channels (x16) Temperature sensor controlled self refresh rate t x16/x8 and 2-channel/pseudo channel (PC) mode Digital RAS lockout configurations set at reset Ondie termination (ODT) for all highspeed inputs Single ended interfaces per channel for command/ Pseudo open drain (POD135 and POD125) compati- address (CA) and data ble outputs Differential clock input CK t/CK c for CA per 2 ODT and output driver strength auto calibration channels with external resistor ZQ pin (120) Two differential clock inputs WCK t/WCK c per Internal V with DFE for data inputs, with input REF channel for data (DQ, DBI n, EDC) receiver characteristics programmable per pin Double data rate (DDR) command/address (CK) Selectable external or internal V for CA inputs REF Quad data rate (QDR) and double data rate (DDR) programmable V offsets for internal V REF REF data (WCK), depending on operating frequency Vendor ID for device identification 16n prefetch architecture with 256 bits per array IEEE 1149.1 compliant boundary scan read or write access 180-ball BGA package 16 internal banks Lead-free (RoHS-compliant) and halogen-free t t t 4 bank groups for CCDL = 3 CK and 4 CK packaging Programmable READ latency T = 0C to +95C C Programmable WRITE latency Write data mask function via CA bus with single and 1 Options Marking double byte mask granularity Organization Data bus inversion (DBI) and CA bus inversion 512 Meg 32 (words bits) 512M32 (CABI) FBGA package Input/output PLL 180-ball (12.0mm 14.0mm) KPA CA bus training: CA input monitoring via DQ/ Timing maximum data rate DBI n/EDC signals 14 Gb/s -14 WCK2CK clock training with phase information via 16 Gb/s -16 EDC signals Operating temperature Data read and write training via read FIFO (depth = Commercial (0C T +95C) None C 6) Revision :B Read/write data transmission integrity secured by cyclic redundancy check 1. Not all options listed can be combined to Note: Programmable CRC READ latency define an offered product. Use the part Programmable CRC WRITE latency catalog search on 16Gb: 2 Channels x16/x8 GDDR6 SGRAM Features Figure 1: Part Numbering MT 61 K 512M32 KPA-16 :B Micron Memory Revision B Product Family Temperature 61 = GDDR6 SGRAM None = Commercial Data Rate Operating Voltage -14 = 14 Gb/s K = 1.35V -16 = 16 Gb/s Configuration 512M32 = 512 Meg x 32 Package KPA = 180-ball FBGA, 12.0mm x 14.0mm FBGA Part Marking Decoder Due to space limitations, FBGA-packaged components have an abbreviated part marking that is different from the part number. For a quick conversion of an FBGA code, see the FBGA Part Marking Decoder on Microns web site: