N25Q128 128Mb 3V, Multiple I/O, 4KB Subsector Erase, XiP Enabled, Serial Flash Memory with 108 MHz SPI Bus Interface JEDEC standard two-byte signature Features (BA18h) SPI-compatible serial bus interface Additional 2 Extended Device ID (EDID) bytes to identify device factory options 108 MHz (maximum) clock frequency Unique ID code (UID) with 14 bytes read- 2.7 V to 3.6 V single supply voltage only Supports legacy SPI protocol and new Quad More than 100,000 program/erase cycles per I/O or Dual I/O SPI protocol sector Quad/Dual I/O instructions resulting in an More than 20 years data retention equivalent clock frequency up to 432 MHz: Packages (all packages RoHS compliant) XIP mode for all three protocols F7 = VDFPN8 6 x 5 mm Sawn (MLP 6 x 5 Configurable via volatile or non-volatile Sawn) registers: enables XiP mode directly after F8 = VDFPN8 8 x 6 mm (MLP8) power on 12 = TBGA24 6 x 8 mm Program/Erase suspend instructions SE = SO8W (SO8 208 mils body width) Continuous read (entire memory) via single SF = SO16 (300 mils body width) instruction: Fast Read Quad or Dual Output Fast Read Quad or Dual I/O Fast Read Flexible to fit application: Configurable number of dummy cycles Output buffer configurable Reset function (upon customer request) 64-byte user-lockable, one-time programmable (OTP) area Erase capability Subsector (4-Kbyte) granularity in the entire memory array Sector (64-Kbyte) granularity Write protections Software write protection applicable to every 64-Kbyte sector (volatile lock bit) Hardware write protection: protected area size defined by non-volatile bits (BP0, BP1, BP2, BP3 and TB bit) Additional smart protections available upon customer request Electronic signature February 2011 Rev 7 1/157 Micron Technology, Inc., reserves the right to change products or specifications without notice. 2010 Micron Technology, Inc. All rights reserved.Contents N25Q128 - 3 V Contents 1 Description 12 2 Signal descriptions . 15 2.1 Serial data output (DQ1) . 15 2.2 Serial data input (DQ0) . 15 2.3 Serial Clock (C) 15 2.4 Chip Select (S) . 15 2.5 Hold (HOLD) or Reset (Reset) . 16 2.6 Write protect/enhanced program supply voltage (W/VPP), DQ2 . 17 2.7 V supply voltage 17 CC 2.8 V ground 17 SS 3 SPI Modes 18 4 SPI Protocols 20 4.1 Selecting and Enabling a Protocol 20 4.2 Exiting DIO-SPI or QIO-SPI Protocols . 20 4.3 Extended SPI protocol . 20 4.4 Dual I/O SPI (DIO-SPI) protocol 20 4.5 Quad SPI (QIO-SPI) protocol 21 5 Operating features . 23 5.1 Extended SPI Protocol Operating features . 23 5.1.1 Read Operations 23 5.1.2 Page programming 23 5.1.3 Dual input fast program . 23 5.1.4 Dual Input Extended Fast Program 23 5.1.5 Quad Input Fast Program . 24 5.1.6 Quad Input Extended Fast Program . 24 5.1.7 Subsector erase, sector erase and bulk erase . 24 5.1.8 Polling during a write, program or erase cycle 24 5.1.9 Active power and standby power modes 25 5.1.10 Hold (or Reset) condition 25 2/157 Micron Technology, Inc., reserves the right to change products or specifications without notice. 2010 Micron Technology, Inc. All rights reserved.