520N-MX PCIe FPGA Board Tool Flow Flexibility for Software- Stratix 10 FPGA Board with 16GB HBM2 or Hardware-Based Development Powerful solution for accelerating memory-bound applications Designed for compute acceleration, the 520N-MX is a PCIe board featuring OpenCL support for software- Intels Stratix 10 MX2100 FPGA with integrated HBM2 memory. The size and orientated customers speed of HBM2 (16GB at up to 512GB/s) enables acceleration of memory-bound Abstration for faster development applications. The boards 100G QSFP28s are ideal for clustering, and OCuLink Push-button flow for FPGA connectors allow expansion. executable, driver, and API Add optimized HDL IP cores to Both traditional HDL and higher abstraction C, C++ and OpenCL designs as libraries OpenCL-based tool flows are supported. Deliverables include an optimized board support package (BSP) for Traditional VHDL/Verilog support for the Intel OpenCL SDK. hardware-orientated customers Hand-code for ultimate performance The 520N-MX features a Board Management High-Level Synthesis (HLS) available for Controller (BMC) for advanced system monitoring rapid development and control, which greatly simplifies platform FPGA card designed to support standard integration and management. Intel IP cores for Stratix 10 Intel Stratix 10 16GB HBM2 OpenCL key features MX2100 up to 512GB/s BSP USB for BMC, FPGA JTAG, and FPGA UART Board Management Controller for 4x QSFP28s for 400Gbps system monitoring and control board-to-board bandwidth OCuLink Expansion Ports Optimize the 520N-MX for your application with expansion: Board-to-board interconnect NVMe access for storage acceleration Connect to accessory boards for customization options Includes GPIO Inquire about customized Molex connectors/cables as required for your application. 2x DIMMs for up to 256 GBytes DDR4, 1152 Mbits QDR-II+, or Intel Optane 3D-XPoint 14nm FPGA with 2.1 million LEs, Gen3 x16 PCIe 16GB integrated HBM2Additional Services Take advantage of BittWares range of design, integration, and support options Customization Server Integration Application Optimization Service and Support Additional specification options Available pre-integrated Ask about our services to help you BittWare Developer Site or accessory boards to meet in our TeraBox servers in a port, optimize, and benchmark provides online documentation your exact needs. range of configurations. your application. and issue tracking. Board Specifications FPGA Intel Stratix 10 MX Cooling Standard: double-width active heatsink (with fan) MX2100 in an F2597 package Optional: double-width passive heatsink 16GBytes on-chip High Bandwidth Memory Optional: double-width liquid cooling (HBM2) DRAM, 410 GB/s (speed grade 2) Electrical On-board power derived from 12V PCIe slot & two Core speed grade -2: I/O speed grade -2 AUX connectors (one 8-pin, one 6-pin) Contact BittWare for other Stratix 10 MX options Power dissipation is application dependent Typical max power consumption 225W On-board Flash 2Gbit Flash memory for booting FPGA Environmental Operating temperature: 5C to 35C External memory 2x 288-pin DIMM slots each fitted with 16GB modules by default, i.e., 32GB total on board Quality Manufactured to ISO9001:2015 IPC-A-610-Class III (options up to 256GB total) RoHS compliant Contact BittWare for QDR-II+ & Intel Optane CE, FCC & ICES approvals (3D-Xpoint) DIMM options Form factor Standard-height PCIe dual-slot board Host interface x16 Gen3 interface direct to FPGA, connected to 4.376 x 10.5 inches (111 x 266.7 mm) PCIe hard IP QSFP cages 4 QSFP28 cages on front panel connected directly to FPGA via 16 transceivers User programmable low jitter clocking supporting Development Tools 10/25/40/100GbE FPGA BIST - Built-In Self-Test for CentOS 7 provided with Each QSFP28 can be independently clocked development source code (pinout, gateware, PCIe driver & host test Jitter cleaner for network recovered clocking application) 2 QSFP28s have available 100GbE MAC hard IP Application Supported design flows - Intel FPGA OpenCL SDK, OCuLink 2x edge connectors (A, B) 12.5G per lane development Intel High-Level Synthesis (C/C++) & Quartus Prime (default) each supports PCIe Gen 3 x8 hard IP, Pro (HDL, Verilog, VHDL, etc.) GPIO, and PCIe master and optional input clocking 2x inner connectors (C, D) 25G per lane Deliverables (optional) 1x 100GbE MAC hard IP per OCuLink 520N-MX FPGA board USB cable (front panel access) Board Voltage, current, temperature monitoring Management Power sequencing and reset Built-In Self-Test (BIST) Controller OpenCL HPC Board Support Package (BSP) Field upgrades 1-year access to online Developer Site FPGA configuration and control Clock configuration 1-year hardware warranty Low bandwidth BMC-FPGA comms with SPI link USB 2.0 PLDM support Voltage overrides To learn more, visit www.BittWare.com Rev 2021.05.24 May 2021 BittWare 2021 Stratix 10 is a registered trademark of Intel Corp. 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