XUP-P3R PCIe FPGA Board UltraScale+ PCIe board with Quad Tool Flow Flexibility for Software- or Hardware-Based Development QSFP and 512 GBytes DDR4 SDAccel support for software-orientated BittWares XUP-P3R is a 3/4-length PCIe x16 card based on the Xilinx Virtex customers UltraScale+ FPGA. The UltraScale+ devices deliver high-performance, high- Abstration for faster development bandwidth, and reduced latency for systems demanding massive data flow Compiler, debugger, and prolefi r with and packet processing. The board offers extensive memory configurations with support for standard OpenCL APIs supporting up to 512 GBytes of memory, sophisticated clocking and timing Add optimized HDL IP cores to OpenCL options, and four front panel QSFP cages, each supporting up to 100 Gbps designs as libraries (4x25) - including 100GbE. Traditional VHDL/Verilog support for The XUP-P3R also incorporates a Board Management Controller (BMC) for hardware-orientated customers advanced system monitoring, which greatly simplifies platform integration Hand-code for ultimate performance and management. All of these features combine to make the XUP-P3R High-Level Synthesis (HLS) available for ideal for a wide range of data center applications, including network rapid development processing and security, acceleration, storage, broadcast, and SigInt. FPGA card designed to support standard Xilinx IP cores for UltraScale+ Up to Up to VU9P: 4x 2.5 million LCs 512 GBytes 100GbE key features FPGA by Xilinx via 4 QSFP28 DDR4 Board Management Controller for Intelligent Platform Management 4x QSFP28s for 4x 40/100GbE or 16x 10/25GbE USB for BMC, FPGA JTAG, and FPGA UART Serial Expansion Interface Optimize the XUP-P3R for your application with expansion: Board-to-board interconnect Connect to accessory boards for customization options such as x16 PCIe or 4x 100G Includes GPIO Inquire about customized Molex connectors/cables as required for your application. 4x DIMMs for up to 16nm FPGA 512 GBytes DDR4 or with up to 2.5 million LCs Gen3 x16 PCIe 2304 Mbits QDR-II+Additional Services Take advantage of BittWares range of design, integration, and support options Customization Server Integration Application Optimization Service and Support Additional specification options Available pre-integrated Ask about our services to help you BittWare Developer Site or accessory boards to meet in our TeraBox servers in a port, optimize, and benchmark provides online documentation your exact needs. range of configurations. your application. and issue tracking. Board Specifications Board Voltage, current, temperature monitoring FPGA Virtex UltraScale+ Management Power sequencing and reset VU9P Controller Field upgrades Core speed grade - 2 FPGA configuration and control Contact BittWare for additional FPGA options Clock configuration 2 * I C bus access External memory 4 DIMM sites, each supporting : USB 2.0 Up to 128 GBytes DDR4 x72 with ECC Voltage overrides Up to 576 Mbits dual QDR-II+ x18 (2 indepen- dent 288 Mbit banks) Cooling Standard: double-width active fan and heatsink Host interface x16 Gen3 interface direct to FPGA Optional: double-width passive heatsink Optional: double-width advanced passive cooling USB header Micro USB: (USB 2.0) for debug and programming with heatpipes FPGA and Flash Electrical On-board power derived from 12V PCIe slot & an Serial expansion Expansion interface to FPGA via 20x GTY transceiv- AUX connector (6-pin) port (SEP) ers (optional requires second slot) Power dissipation is application dependent 14x GPIO signals to the FPGA Environmental Operating temperature 5C to 35C QSFP cages 4 QSFP28 (zQSFP) cages on front panel connected directly to FPGA via 16 transceivers Size 3/4-length, standard-height PCIe dual-slot card Each supports 100GbE, 40GbE, 4x 25GbE, or 4x 9.4 x 4.37 inches 10GbE and can be combined for 400GbE On-board Flash Flash memory for booting FPGA Development Tools FPGA development FPGA Examples - example Vivado projects * DIMM sites 1/2 and sites 3/4 must have the same memory type, or be empty. Application HDL/verilog development BittWorks II Toolkit - host, command, and debug tools for BittWare hardware Xilinx Vivado Design Suite OpenCL - Xilinx SDAccel Development Environ- ment, SDAccel Platform Release and pre-built examples for XUP-P3R To learn more, visit www.BittWare.com Rev 2019.12.19 December 2019 BittWare 2019 UltraScale, Virtex, and Vivado are registered trademarks of Xilinx Corp. All other products are the trademarks or registered trademarks of their respective holders.