XUP-VV8 PCIe FPGA Board 8x 100GbE Network Ports and VU13P FPGA The XUP-VV8 offers a large Xilinx FPGA in a 3/4-length PCIe board featuring QSFP-DD (double-density) cages for maximum port density. Using the Virtex UltraScale+ VU13P or VU9P FPGA, the board supports up to 8x 100GbE or 32x 10/25GbE. The FPGA provides large logic and memory resourcesup to 3.8M logic cells and 455Mb embedded memory. The board also provides a jitter cleaner to support synchronous ethernet. The board can be configured as single width for users who dont need external memory on the DIMMs. Module connects to one of the QSFP-DD cages on XUP-VV8 Xilinx VU13P FPGA: lidless package is used by BittWares Viper thermal management for enhanced cooling performance Breakout QSFP28 to 2x 100GbE modules Air or Up to 3.8M Logic Four QSFP-DDs up to 8x 100GbE Cells and 455Mb Liquid key features or 32x 10/25GbE Embedded RAM Cooled Jitter cleaner for Board Management 4x DIMMs for up to synchronous ethernet Controller for system moni- 512 GBytes DDR4 or 4x QSFP-DDs for toring and control 2.3 Gbits QDR-II+ 8x 100GbE OCuLink Expansion Ports Optimize the XUP-VV8 for your application with expansion: Board-to-board interconnect Connect to accessory boards for customization options Inquire about customized Molex connectors/cables as required for your application. On-board USB-JTAG 16nm FPGA 1x PCIe Gen3 x16 interface with up to 3.8 million LCsAdditional Services Take advantage of BittWares range of design, integration, and support options Customization Server Integration Application Optimization Service and Support Additional specification options Available pre-integrated Ask about our services to help you BittWare Developer Site or accessory boards to meet in our TeraBox servers in a port, optimize, and benchmark provides online documentation your exact needs. range of configurations. your application. and issue tracking. Board Specifications Board Voltage, current, temperature monitoring Management Power sequencing and reset FPGA Virtex UltraScale+ Controller Field upgrades VU9P or VU13P in D2104 package FPGA configuration and control Core speed grade - 2 Clock configuration Contact BittWare for other FPGA options 2 I C bus access USB 2.0 On-board Flash Flash memory for booting FPGA Voltage overrides External memory 4 DIMM sites, each supporting: Cooling Standard: dual-width passive heatsink Up to 128 GBytes DDR4 x72 with ECC Optional: single-width passive heatsink* Up to 576 Mbits dual QDR-II+ x18 (2 indepen- Optional: dual-width active heatsink dent 288 Mbit banks) Optional: dual-width liquid cooling Host interface x16 Gen3 interface direct to FPGA Electrical On-board power derived from 12V PCIe slot & two USB port Micro USB: access to BMC, FPGA JTAG, and FPGA AUX connectors (8-pin) UART Power dissipation is application dependent Timestamp 1 PPS input and 10MHz clock input Environmental Operating temperature 5C to 35C OCuLink 2 OCuLink on rear edge, each connected to FPGA Form factor 3/4-length, standard-height PCIe dual-width board via 4x GTY transceivers Single-width option* 10 x 4.37 inches (254 x 111.15 mm) QSFP cages 4 QSFP-DD cages on front panel Each supports 2x 100GbE, 2x 40GbE, 8x 25GbE, or 8x 10GbE Jitter cleaner for network recovered clocking Development Tools System BittWorks II Toolkit - host, command, and debug development tools for BittWare hardware FPGA development FPGA Examples - example Vivado projects, avail- able with the BittWorks II Toolkit Xilinx Tools - Vivado Design Suite * Available on boards with no external memory To learn more, visit www.BittWare.com Rev 2020.02.11 Febrary 2020 BittWare, Inc. 2020 UltraScale, Virtex, and Vivado are registered trademarks of Xilinx Corp. All other products are the trademarks or registered trademarks of their respective holders.