ChipWhisperer Embedded Security Analysis Tools CW308 UFO Targets NewAE Technology Cypress PSOC62 UFO Target NewAE Technology Inc. Product Datasheet newae.com e PSTh oC62 board features the CY8C6247BZI-D44 from Cypress Semiconductors. This device features multiple secure boot fea - tures, and a seperate Cortex-M0 security code in addition to the Cortex-M4 main processor. e PCB lTh ayout should be compatible with the PSoC64 - the PSoC64 features effectively the PSoC62 with pre-programmed secure core memory. This board requires an external JTAG/SWD programmer (such as OpenOCD or J-Link) for use, as does not include a bootloader. e desigTh n files are available as part of the open-source ChipWhis - perer example targets. CW308 UFO Baseboard REQUIRED for use JTAG Programmer REQUIRED for use Product Highlights CY8C6247BZI-D44 (PSoC62) in 124-BGA package features many security features, including E-Fuse boot options, boot verification, and a security co-processor. Total of 1MB of FLASH Memory, 288 KB SRAM, and 1KB EFUSE memory. Cortex-M4F main processor, and Cortex-M0+ co-processor used for security and secure boot, boots from ROM first. Multiple cryptographic accelerators including AES, 3DES, RSA, SHA-512, SHA-256 and ECC. Ordering Summary NAE-CW308T-PSOC62 Cypress PSOC62 (CY8C6247BZI-D44) UFO Target Board. Product Links Full Documentation Schematic 1 2 3 4 U1A U1B E3 F1 RST P0 0 XRES SJ1 E2 VCC3V3 P0 1 A A E1 H13 A12 J2 P0 2 P8 0 VDDA VIND1 F3 H12 A13 P0 3 P8 1 VDDIOA F2 H11 K1 100n P0 4 P8 2 NC1 See K1/K2/K3 C1 G3 G13 K2 P0 5 P8 3 NC2 Note G12 K3 P8 4 NC3 G2 G11 A1 P1 0 P8 5 VDDD G1 F13 K12 GND P1 1 P8 6 VDDIO1 H3 F12 C2 P1 2 P8 7 VDDIO=2.5V for E-Fuse H2 B13 P1 3 VREF H1 E11 3 P1 4 P9 0 100n J3 E12 VCC2V5 2 C4 P1 5 P9 1 VDDIO0 E13 1 GND P9 2 RX M2 F11 100n SHUNTL SJ2 P2 0 P9 3 C4 TX N2 D13 P2 1 P9 4 L3 D12 L4 P2 2 P9 5 VDDIO2 M3 D11 A2 R1 10R SHUNTH P2 3 P9 6 VCCD N3 C13 GND P2 4 P9 7 N1 DNM P2 5 C3 M4 C12 1 2 J1 P2 6 P10 0 Pin C11 grounded for VDD NS GPIO3 N4 A11 SJ3 P2 7 P10 1 routing reasons only. B11 P10 2 B B L5 C11 B12 GND P3 0 P10 3 VSS0 M5 A10 M1 C3 100n 2u2 P3 1 P10 4 VDDUSB VSS1 GPIO4 N5 B10 100n D4 C5 C6 P3 2 P10 5 VSS2 C14 L6 C10 D10 P3 3 P10 6 VSS3 M6 A9 GND K4 P3 4 P10 7 VSS4 N6 D1 K10 P3 5 VBACKUP VSS5 B9 GND P11 0 L7 C9 GND P4 0 P11 1 M7 A8 CY8C6247BZI-D44 P4 1 P11 2 B8 P11 3 VIND1 is swithing reg output, VDD NS is MOSI N7 C8 P5 0 P11 4 switching reg input. MISO L8 A7 P5 1 P11 5 SCK M8 B7 GND P5 2 P11 6 N8 C7 P5 3 P11 7 L9 P5 4 M9 A6 P5 5 P12 0 CS N9 B6 P5 6 P12 1 N10 C6 VCC3V3 VCC2V5 P5 7 P12 2 A5 P12 3 M10 B5 P6 0 P12 4 L10 C5 100n 100n 100n 100n 2u2 2u2 2u2 P6 1 P12 5 L11 A4 XIN C7 C8 C9 C10 C11 C12 C13 C C P6 2 P12 6 M11 B4 P6 3 P12 7 SWO N11 P6 4 M12 B1 GND GND P6 5 P13 0 SWDIO N12 A3 P6 6 P13 1 SWCLK M13 B3 P6 7 P13 2 B2 P13 3 L13 C2 P7 0 P13 4 VCC3V3 L12 C1 P7 1 P13 5 K13 D3 P7 2 P13 6 N13 D2 P7 3 P13 7 K11 P7 4 K1/K2/K3 connection is not actually NC. This symbol used was released by Cypress which has K1/K2/K3 as J13 L2 P7 5 USBDP NC. But the x6/x7 and xA/x8 claim different outputs here from the switching reg. As we are not using the J12 L1 P7 6 USBDM switching reg we choose to ignore these. J11 P7 7 CY8C6247BZI-D44 BGA is 0.65mm spacing, but the breakout done with 5 mil trace/space and 0.3mm drill vias to make PCB fab D D easier, limits usage of pins to outer two rows + some of the inner balls. Title: CW308T-PSoC62 Microcontroller Approved: YES Rev: Project: License: 01 PSoC62 Target GPL Date: 2019-10-29 Time: 10:05:01 PM Sheet12of Copyright NewAE Technology Inc. NewAE.com File: CW308T PSoC62 MCU.SchDoc 1 2 3 4 NewAE Technology Inc. Your friendly embedded security arsonist. newae.com 2 1 CW308T-PSOC62 Datasheet 2 Last Update: 2020-MAY-22