74AHC00 74AHCT00 Quad 2-input NAND gate Rev. 5 26 May 2020 Product data sheet 1. General description The 74AHC00 74AHCT00 are quad 2-input NAND gates. Inputs are overvoltage tolerant. This feature allows the use of these devices as translators in mixed voltage environments. 2. Features Wide supply voltage range from 2.0 V to 5.5 V Input levels: For 74AHC00: CMOS level For 74AHCT00: TTL level Balanced propagation delays All inputs have Schmitt-trigger actions Overvoltage tolerant inputs to 5.5 V High noise immunity CMOS low power dissipation ESD protection: HBM EIA/JESD22-A114E exceeds 2000 V MM EIA/JESD22-A115-A exceeds 200 V CDM EIA/JESD22-C101C exceeds 1000 V Latch-up performance exceeds 100 mA per JESD 78 Class II Level A Multiple package options Specified from -40 C to +85 C and from -40 C to +125 C 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74AHC00D -40 C to +125 C SO14 plastic small outline package 14 leads SOT108-1 body width 3.9 mm 74AHCT00D 74AHC00PW -40 C to +125 C TSSOP14 plastic thin shrink small outline package 14 leads SOT402-1 body width 4.4 mm 74AHCT00PW 74AHC00BQ -40 C to +125 C DHVQFN14 plastic dual in-line compatible thermal SOT762-1 enhanced very thin quad flat package no leads 74AHCT00BQ 14 terminals body 2.5 3 0.85 mmNexperia 74AHC00 74AHCT00 Quad 2-input NAND gate 4. Functional diagram 1 3 & 1 1A 2 1Y 3 2 1B 4 4 2A 6 & 2Y 6 5 5 2B 9 9 3A 3Y 8 8 & 10 3B 10 A 12 4A 12 4Y 11 Y 11 13 4B & 13 B mna212 mna246 mna211 Fig. 1. Logic symbol Fig. 2. IEC logic symbol Fig. 3. Logic diagram (one gate) 5. Pinning information 5.1. Pinning terminal 1 index area 1B 2 13 4B 1Y 3 12 4A 2A 4 00 11 4Y 1A 1 14 V CC 5 10 2B (1) 3B GND 1B 2 13 4B 2Y 6 9 3A 1Y 3 12 4A 2A 4 00 11 4Y 001aac939 2B 5 10 3B 2Y 6 9 3A Transparent top view GND 7 8 3Y (1) This is not a ground pin. There is no electrical or mechanical requirement to solder the pad. In case 001aac938 soldered, the solder land should remain floating or connected to GND Fig. 4. Pin configuration SOT108-1 (SO14) and SOT402-1 (TSSOP14) Fig. 5. Pin configuration SOT762-1 (DHVQFN14) 5.2. Pin description Table 2. Pin description Symbol Pin Description 1A, 2A, 3A, 4A 1, 4, 9, 12 data inputs 1B, 2B, 3B, 4B 2, 5, 10, 13 data inputs 1Y, 2Y, 3Y, 4Y 3, 6, 8, 11 data outputs GND 7 ground (0 V) V 14 supply voltage CC 74AHC AHCT00 All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2020. All rights reserved Product data sheet Rev. 5 26 May 2020 2 / 12 GND 7 1 1A 3Y 8 14 V CC