74AHC08-Q100 74AHCT08-Q100 Quad 2-input AND gate Rev. 2 26 May 2020 Product data sheet 1. General description The 74AHC08-Q100 74AHCT08-Q100 are quad 2-input AND gates. Inputs are overvoltage tolerant. This feature allows the use of these devices as translators in mixed voltage environments. This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications. 2. Features and benefits Automotive product qualification in accordance with AEC-Q100 (Grade 1) Specified from -40 C to +85 C and from -40 C to +125 C Wide supply voltage range from 2.0 V to 5.5 V Input levels: For 74AHC08-Q100: CMOS level For 74AHCT08-Q100: TTL level Balanced propagation delays All inputs have a Schmitt-trigger action Overvoltage tolerant inputs to 5.5 V High noise immunity CMOS low power dissipation ESD protection: MIL-STD-883, method 3015 exceeds 2000 V HBM EIA/JESD22-A114F exceeds 2000 V MM EIA/JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 ) Latch-up performance exceeds 100 mA per JESD 78 Class II Level A Multiple package options DHVQFN package with Side-Wettable Flanks enabling Automatic Optical Inspection (AOI) of solder joints 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74AHC08D-Q100 -40 C to +125 C SO14 plastic small outline package 14 leads SOT108-1 body width 3.9 mm 74AHCT08D-Q100 74AHC08PW-Q100 -40 C to +125 C TSSOP14 plastic thin shrink small outline package 14 leads SOT402-1 body width 4.4 mm 74AHCT08PW-Q100 74AHC08BQ-Q100 -40 C to +125 C DHVQFN14 plastic dual in-line compatible thermal SOT762-1 enhanced very thin quad flat package no leads 74AHCT08BQ-Q100 14 terminals body 2.5 3 0.85 mmNexperia 74AHC08-Q100 74AHCT08-Q100 Quad 2-input AND gate 4. Functional diagram 1 & 3 2 4 & 6 1 1A 1Y 3 5 2 1B 4 2A 2Y 6 9 5 2B & 8 10 9 3A 3Y 8 10 3B A 12 12 4A & 11 4Y 11 Y 13 4B 13 B mna222 mna223 mna221 Fig. 1. Logic symbol Fig. 2. IEC logic symbol Fig. 3. Logic diagram (one gate) 5. Pinning information 5.1. Pinning 74AHC08 74AHCT08 terminal 1 index area 74AHC08 74AHCT08 1B 2 13 4B 1Y 3 12 4A 1A 1 14 V CC 2A 4 11 4Y 1B 2 13 4B 5 10 2B (1) 3B GND 1Y 3 12 4A 2Y 6 9 3A 4 11 2A 4Y 2B 5 10 3B aaa-031694 Transparent top view 2Y 6 9 3A (1) This is not a ground pin. There is no electrical or GND 7 8 3Y mechanical requirement to solder the pad. In case aaa-031693 soldered, the solder land should remain floating or connected to GND Fig. 4. Pin configuration SOT108-1 (SO14) and SOT402-1 (TSSOP14) Fig. 5. Pin configuration SOT762-1 (DHVQFN14) 5.2. Pin description Table 2. Pin description Symbol Pin Description 1A, 2A, 3A, 4A 1, 4, 9, 12 data inputs 1B, 2B, 3B, 4B 2, 5, 10, 13 data inputs 1Y, 2Y, 3Y, 4Y 3, 6, 8, 11 data outputs GND 7 ground (0 V) V 14 supply voltage CC 74AHC AHCT08 Q100 All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2020. All rights reserved Product data sheet Rev. 2 26 May 2020 2 / 12 GND 7 1 1A 3Y 8 14 V CC