74AHC273BQ Nexperia

74AHC273 74AHCT273 Octal D-type ip-op with reset positive-edge trigger Rev. 03 13 May 2008 Product data sheet 1. General description The 74AHC273 74AHCT273 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). It is specied in compliance with JEDEC standard No. 7-A. The 74AHC273 74AHCT273 has eight edge-triggered, D-type ip-ops with individual D inputs and Q outputs. The common clock (CP) and master reset (MR) inputs, load and reset (clear) all ip-ops simultaneously. The state of each D input, one set-up time before the LOW-to-HIGH clock transition, is transferred to the corresponding output (Qn) of the ip-op. All outputs will be forced LOW, independent of clock or data inputs, by a LOW on the MR input. The device is useful for applications where only the true output is required and the clock and master reset are common to all storage elements. 2. Features n Balanced propagation delays n All inputs have Schmitt-trigger actions n Inputs accept voltages higher than V CC n Ideal buffer for MOS microcontroller or memory n Common clock and master reset n Related product versions: u 74AHC377 74AHCT377 for clock enable version u 74AHC373 74AHCT373 for transparent latch version u 74AHC374 74AHCT374 for 3-state version n Input levels: u For 74AHC273: CMOS level u For 74AHCT273: TTL level n ESD protection: u HBM EIA/JESD22-A114E exceeds 2000 V u MM EIA/JESD22-A115-A exceeds 200 V u CDM EIA/JESD22-C101C exceeds 1000 V n Multiple package options n Specied from - 40 C to +85 C and from - 40 C to +125 C74AHC273 74AHCT273 NXP Semiconductors Octal D-type ip-op with reset positive-edge trigger 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74AHC273 74AHC273D - 40 C to +125 C SO20 plastic small outline package 20 leads SOT163-1 body width 7.5 mm 74AHC273PW - 40 C to +125 C TSSOP20 plastic thin shrink small outline package 20 leads SOT360-1 body width 4.4 mm 74AHC273BQ - 40 C to +125 C DHVQFN20 plastic dual in-line compatible thermal enhanced very SOT764-1 thin quad at package no leads 20 terminals body 2.5 4.5 0.85 mm 74AHCT273 74AHCT273D - 40 C to +125 C SO20 plastic small outline package 20 leads SOT163-1 body width 7.5 mm 74AHCT273PW - 40 C to +125 C TSSOP20 plastic thin shrink small outline package 20 leads SOT360-1 body width 4.4 mm 74AHCT273BQ - 40 C to +125 C DHVQFN20 plastic dual in-line compatible thermal enhanced very SOT764-1 thin quad at package no leads 20 terminals body 2.5 4.5 0.85 mm 4. Functional diagram 11 CP C1 1 R MR 11 3 2 D0 1D Q0 CP 3 2 D0 Q0 4 5 D1 Q1 4 5 D1 Q1 7 6 7 6 D2 Q2 D2 Q2 8 9 8 9 D3 Q3 D3 Q3 13 12 13 12 D4 Q4 D4 Q4 14 15 14 15 D5 Q5 D5 Q5 17 16 D6 Q6 17 16 D6 Q6 18 19 D7 Q7 18 19 MR D7 Q7 1 mna764 mna763 Fig 1. Logic symbol Fig 2. IEC logic symbol 74AHC AHCT273 3 NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 13 May 2008 2 of 18