74AHC74PW,112 Nexperia

74AHC74 74AHCT74 Dual D-type flip-flop with set and reset positive-edge trigger Rev. 8 22 April 2020 Product data sheet 1. General description The 74AHC74 74AHCT74 is a high-speed Si-gate CMOS device and is pin compatible with Low-Power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard No. 7-A. The 74AHC74 74AHCT74 is a dual positive-edge triggered, D-type flip-flop with individual data inputs (D), clock inputs (CP), set inputs (SD) and reset inputs (RD). It also has complementary outputs (Q and Q). The set and reset are asynchronous active LOW inputs that operate independent of the clock input. Information on the data input is transferred to the Q output on the LOW to HIGH transition of the clock pulse. The data inputs must be stable one set-up time prior to the LOW to HIGH clock transition for predictable operation. Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times. 2. Features and benefits Balanced propagation delays All inputs have Schmitt-trigger actions Inputs accept voltages higher than V CC Input levels: For 74AHC74: CMOS level For 74AHCT74: TTL level ESD protection: HBM EIA/JESD22-A114E exceeds 2000 V MM EIA/JESD22-A115-A exceeds 200 V CDM EIA/JESD22-C101C exceeds 1000 V Multiple package options Specified from -40 C to +85 C and from -40 C to +125 C 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74AHC74D -40 C to +125 C SO14 plastic small outline package 14 leads SOT108-1 body width 3.9 mm 74AHCT74D 74AHC74PW -40 C to +125 C TSSOP14 plastic thin shrink small outline package 14 leads SOT402-1 body width 4.4 mm 74AHCT74PW 74AHC74BQ -40 C to +125 C DHVQFN14 plastic dual in-line compatible thermal enhanced SOT762-1 very thin quad flat package no leads 14 terminals 74AHCT74BQ body 2.5 3 0.85 mmNexperia 74AHC74 74AHCT74 Dual D-type flip-flop with set and reset positive-edge trigger 4. Functional diagram 1SD 4 SD 1Q 1D 2 Q D 5 1CP 3 CP FF 1Q Q 6 RD 4 4 10 S 5 1RD 3 1 C1 1SD 2SD 2 2SD 1D 6 10 SD 1 2 1D 1Q 5 R D Q 12 2D 2Q 9 SD 2Q 2D 3 1CP 12 D Q 9 CP 10 11 2CP FF S 2CP 9 1Q 6 11 CP 11 Q C1 8 FF 2Q 2Q 12 RD Q 8 1D 8 13 RD 1RD 2RD R 2RD 1 13 mna420 mna418 13 mna419 Fig. 1. Functional diagram Fig. 2. Logic symbol Fig. 3. IEC logic symbol Q C C C C C C D Q C C RD SD mna421 CP C C Fig. 4. Logic diagram (one flip-flop) 74AHC AHCT74 All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2020. All rights reserved Product data sheet Rev. 8 22 April 2020 2 / 15