74AHCT157BQ Nexperia

74AHC157 74AHCT157 Quad 2-input multiplexer Rev. 02 9 November 2007 Product data sheet 1. General description The 74AHC/AHCT157 are high-speed Si-gate CMOS devices and are pin compatible with Low Power Schottky TTL (LSTTL). They are specied in compliance with JEDEC standard no. 7A. The 74AHC/AHCT157 are quad 2-input multiplexer which select 4 bits of data from two sources under the control of a common data select input (S). The enable input (E) is active LOW. When E is HIGH, all of the outputs (1Y to 4Y) are forced LOW regardless of all other input conditions. Moving the data from two groups of registers to four common output buses is a common use of the 74AHC/AHCT157. The state of the common data select input (S) determines the particular register from which the data comes. It can also be used as function generator. The device is useful for implementing highly irregular logic by generating any four of the 16 different functions of two variables with one variable common. The 74AHC/AHCT157 is logic implementation of a 4-pole, 2-position switch, where the position of the switch is determine by the logic levels applied to S. The logic equations are: 1Y = E (1I1 S + 1I0 S) 2Y = E (2I1 S + 2I0 S) 3Y = E (3I1 S + 3I0 S) 4Y = E (4I1 S + 4I0 S) The 74AHC/AHCT157 is identical to the 74AHC/AHCT158 but has non-inverting (true) outputs. 2. Features Balanced propagation delays All inputs have a Schmitt-trigger action Inputs accepts voltages higher than V CC Multiple input enable for easy expansion Ideal for memory chip select decoding For 74AHC157 only: operates with CMOS input levels For 74AHCT157 only: operates with TTL input levels ESD protection: HBM JESD22-A114E exceeds 2000 V MM JESD22-A115-A exceeds 200 V CDM JESD22-C101C exceeds 1000 V74AHC157 74AHCT157 NXP Semiconductors Quad 2-input multiplexer Multiple package options Specied from - 40 C to +85 C and from - 40 C to +125 C 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74AHC157D - 40 C to +125 C SO16 plastic small outline package 16 leads SOT109-1 body width 3.9 mm 74AHCT157D 74AHC157PW - 40 C to +125 C TSSOP16 plastic thin shrink small outline package 16 leads SOT403-1 body width 4.4 mm 74AHCT157PW 74AHC157BQ - 40 C to +125 C DHVQFN16 plastic dual in-line compatible thermal enhanced SOT763-1 very thin quad at package no leads 16 terminals 74AHCT157BQ body 2.5 3.5 0.85 mm 4. Functional diagram S E 1I1 1Y 1I0 2I1 2Y 2I0 2 3 5 6 11 10 14 13 3I1 3Y 1I0 1I1 2I0 2I1 3I0 3I1 4I0 4I1 3I0 1 S 15 E 4I1 1Y 2Y 3Y 4Y 4Y 4 7 9 12 4I0 mna484 mna481 Fig 1. Logic diagram Fig 2. logic symbol 74AHC AHCT157 2 NXP B.V. 2007. All rights reserved. Product data sheet Rev. 02 9 November 2007 2 of 16