74AHCT3G04GD,125 Nexperia

74AHC3G04 74AHCT3G04 Inverter Rev. 5 4 August 2021 Product data sheet 1. General description The 74AHC3G04 74AHCT3G04 is a triple inverter. Inputs are overvoltage tolerant. This feature allows the use of these devices as translators in mixed voltage environments. The AHC device has CMOS input switching levels and supply voltage range 2 V to 5.5 V. The AHCT device has TTL input switching levels and supply voltage range 4.5 V to 5.5 V. 2. Features and benefits Wide supply voltage range from 2.0 to 5.5 V Overvoltage tolerant inputs to 5.5 V Symmetrical output impedance High noise immunity CMOS low power dissipation Balanced propagation delays Latch-up performance exceeds 100 mA per JESD 78 Class II Level A ESD protection: HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V CDM JESD22-C101C exceeds 1000 V Multiple package options Specified from -40 C to +85 C and from -40 C to +125 C 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74AHC3G04DP -40 C to +125 C TSSOP8 plastic thin shrink small outline package 8 leads SOT505-2 body width 3 mm lead length 0.5 mm 74AHC3G04DC -40 C to +125 C VSSOP8 plastic very thin shrink small outline package SOT765-1 8 leads body width 2.3 mm 74AHCT3G04DC 74AHC3G04GT -40 C to +125 C XSON8 plastic extremely thin small outline package SOT833-1 no leads 8 terminals body 1 1.95 0.5 mmNexperia 74AHC3G04 74AHCT3G04 Inverter 4. Marking Table 2. Marking codes Type number Marking code 1 74AHC3G04DP A04 74AHC3G04DC A04 74AHCT3G04DC C04 74AHC3G04GT A04 1 The pin 1 indicator is located on the lower left corner of the device, below the marking code. 5. Functional diagram 1 1 7 1 1A 1Y 7 1 3 5 3 2A 2Y 5 1 6 3A 3Y 2 6 2 A Y mna720 mna721 mna110 Fig. 1. Logic symbol Fig. 2. IEC logic symbol Fig. 3. Logic diagram (one gate) 6. Pinning information 6.1. Pinning 74AHC3G04 1A 1 8 V CC 74AHC3G04 3Y 2 7 1Y 74AHCT3G04 1A 1 8 V CC 2A 3 6 3A 3Y 2 7 1Y 2A 3 6 3A GND 4 5 2Y GND 4 5 2Y aaa-033057 001aaj514 Transparent top view Fig. 4. Pin configuration SOT505-2 (TSSOP8) and SOT765-1 (VSSOP8) Fig. 5. Pin configuration 833-1 (XSON8) 74AHC AHCT3G04 All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2021. All rights reserved Product data sheet Rev. 5 4 August 2021 2 / 13