74AHCT574BQ Nexperia

74AHC574 74AHCT574 Octal D-type ip-op positive edge-trigger 3-state Rev. 02 24 January 2008 Product data sheet 1. General description The 74AHC574 74AHCT574 are high-speed Si-gate CMOS devices and are pin compatible with Low Power Schottky TTL (LSTTL). They are specied in compliance with JEDEC standard no. 7A. The 74AHC574 74AHCT574 are octal D-type ip-ops featuring separate D-type inputs for each ip-op and 3-state outputs for bus oriented applications. A clock (CP) and an output enable (OE) input are common to all ip-ops. The 8 ip-ops will store the state of their individual D-inputs that meet the set-up and hold times requirements on the LOW-to-HIGH CP transition. When OE is LOW the contents of the 8 ip-ops are available at the outputs. When OE is HIGH, the outputs go to the high-impedance OFF-state. Operation of the OE input does not affect the state of the ip-ops. The 74AHC574 74AHCT574 is functionally identical to the 74AHC564 74AHCT564, but has non-inverting outputs. The 74AHC574 74AHCT574 is functionally identical to the 74AHC374 74AHCT374, but has a different pinning. 2. Features n Balanced propagation delays n All inputs have a Schmitt-trigger action n 3-state non-inverting outputs for bus orientated applications n 8-bit positive, edge-triggered register n Independent register and 3-state buffer operation n Common 3-state output enable input n For 74AHC574 only: operates with CMOS input levels n For 74AHCT574 only: operates with TTL input levels n ESD protection: u HBM JESD22-A114E exceeds 2000 V u MM JESD22-A115-A exceeds 200 V u CDM JESD22-C101C exceeds 1000 V n Multiple package options n Specied from - 40 C to +85 C and from - 40 C to +125 C74AHC574 74AHCT574 NXP Semiconductors Octal D-type ip-op positive edge-trigger 3-state 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74AHC574D - 40 C to +125 C SO20 plastic small outline package 20 leads SOT163-1 body width 7.5 mm 74AHCT574D 74AHC574PW - 40 C to +125 C TSSOP20 plastic thin shrink small outline package 20 leads SOT360-1 body width 4.4 mm 74AHCT574PW 74AHC574BQ - 40 C to +125 C DHVQFN20 plastic dual in-line compatible thermal enhanced SOT764-1 very thin quad at package no leads 20 terminals 74AHCT574BQ body 2.5 4.5 0.85 mm 4. Functional diagram 2 D0 Q0 19 3 D1 Q1 18 D2 4 Q2 17 D3 5 FF1 Q3 16 3-STATE to 6 D4 Q4 15 OUTPUTS FF8 7 D5 Q5 14 Q6 8 D6 13 9 D7 Q7 12 CP 11 1 OE mna800 Fig 1. Functional diagram D0 D1 D2 D3 D4 D5 D6 D7 D Q D Q D Q D Q D Q D Q D Q D Q CP CP CP CP CP CP CP CP FF1 FF2 FF3 FF4 FF5 FF6 FF7 FF8 CP OE Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 001aah077 Fig 2. Logic diagram 74AHC AHCT574 2 NXP B.V. 2008. All rights reserved. Product data sheet Rev. 02 24 January 2008 2 of 18