74AHCT594PW-Q100,1 Nexperia

74AHC594-Q100 74AHCT594-Q100 8-bit shift register with output register Rev. 4 7 July 2021 Product data sheet 1. General description The 74AHC594-Q100 74AHCT594-Q100 is a high-speed Si-gate CMOS device and is pin compatible with Low-Power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard No. 7-A. The 74AHC594-Q100 74AHCT594-Q100 is an 8-bit, non-inverting, serial-in, parallel-out shift register that feeds an 8-bit D-type storage register. Separate clocks (SHCP and STCP) and direct overriding clears (SHR and STR) are provided on both the shift and storage registers. A serial output (Q7S) is provided for cascading purposes. Both the shift and storage register clocks are positive-edge triggered. If the user wishes to connect both clocks together, the shift register will always be one count pulse ahead of the storage register. This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications. 2. Features and benefits Automotive product qualification in accordance with AEC-Q100 (Grade 1) Specified from -40 C to +85 C and from -40 C to +125 C Wide supply voltage range from 2.0 V to 5.5 V Balanced propagation delays All inputs have Schmitt-trigger action Overvoltage tolerant inputs to 5.5 V High noise immunity CMOS low power dissipation 8-bit serial-in, parallel-out shift register with storage Independent direct overriding clears on shift and storage registers Independent clocks for shift and storage registers Latch-up performance exceeds 100 mA per JESD 78 Class II Level A Input levels: For 74AHC594-Q100: CMOS level For 74AHCT594-Q100: TTL level ESD protection: MIL-STD-883, method 3015 exceeds 2000 V HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V (C = 200 pf, R = 0 ) Multiple package options DHVQFN package with Side-Wettable Flanks enabling Automatic Optical Inspection (AOI) of solder joints 3. Applications Serial-to parallel data conversion Remote control holding registerNexperia 74AHC594-Q100 74AHCT594-Q100 8-bit shift register with output register 4. Ordering information Table 1. Ordering information Type number Package Temperature Name Description Version range 74AHC594D-Q100 -40 C to +125 C SO16 plastic small outline package 16 leads SOT109-1 body width 3.9 mm 74AHCT594D-Q100 74AHC594PW-Q100 -40 C to +125 C TSSOP16 plastic thin shrink small outline package 16 leads SOT403-1 body width 4.4 mm 74AHCT594PW-Q100 74AHC594BQ-Q100 -40 C to +125 C DHVQFN16 plastic dual in-line compatible thermal SOT763-1 enhanced very thin quad flat package no leads 74AHCT594BQ-Q100 16 terminals body 2.5 3.5 0.85 mm 5. Functional diagram 14 DS 11 SHCP 8-STAGE SHIFT REGISTER 10 SHR 9 Q7S 12 STCP 8-BIT STORAGE REGISTER 13 STR 15 1 2 3 4 5 6 7 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 mbc320 Fig. 1. Functional diagram SHCP STCP 13 STR R2 12 11 12 STCP C2 9 Q7S 10 SHR R1 SRG8 11 15 Q0 SHCP C1/ Q1 1 14 15 DS 1D 2D Q0 2 Q2 1 Q1 DS 14 3 Q3 2 Q2 4 Q4 3 Q3 4 Q5 5 Q4 5 6 Q6 Q5 6 Q6 7 Q7 7 Q7 10 13 9 Q7S SHR STR mbc319 mbc322 Fig. 2. Logic symbol Fig. 3. IEC logic symbol 74AHC AHCT594 Q100 All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2021. All rights reserved Product data sheet Rev. 4 7 July 2021 2 / 20