Important notice
Dear Customer,
On 7 February 2017 the former NXP Standard Product business became a new company with the
tradename Nexperia. Nexperia is an industry leading supplier of Discrete, Logic and PowerMOS
semiconductors with its focus on the automotive, industrial, computing, consumer and wearable
application markets
In data sheets and application notes which still contain NXP or Philips Semiconductors references, use
the references to Nexperia, as shown below.
Instead of 74ALVT16823
18-bit bus-interface D-type ip-op with reset and enable;
3-state
Rev. 04 2 August 2005 Product data sheet
1. General description
The 74ALVT16823 18-bit bus interface register is designed to eliminate the extra
packages required to buffer existing registers and provide extra data width for wider
data/address paths of buses carrying parity.
The 74ALVT16823 has two 9-bit wide buffered registers with clock enable (pin nCE) and
master reset (pin nMR) which are ideal for parity bus interfacing in high microprogrammed
systems.
The registers are fully edge-triggered. The state of each D input, one set-up time before
the LOW-to-HIGH clock transition is transferred to the corresponding Q output of the
ip-op.
It is designed for V operation from 2.5 V to 3.0 V with I/O compatibility to 5 V.
CC
2. Features
Two sets of high speed parallel registers with positive edge-triggered D-type ip-ops
5 V I/O compatible
Ideal where high speed, light loading, or increased fan-in are required with MOS
microprocessors
Bus hold data inputs eliminate the need for external pull-up resistors to hold unused
inputs
Live insertion and extraction permitted
Power-up 3-state
Power-up reset
No bus current loading when output is tied to 5 V bus
Output capability: +64 mA to - 32 mA
Latch-up protection:
JESD78: exceeds 500 mA
ESD protection:
MIL STD 883, method 3015: exceeds 2000 V
Machine Model: exceeds 200 V