74AUP1G157GM-Q100X Nexperia

74AUP1G157-Q100 Low-power 2-input multiplexer Rev. 2 4 November 2021 Product data sheet 1. General description The 74AUP1G157-Q100 is a single 2-input multiplexer. Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall times. This device ensures a very low static and dynamic power consumption across the entire V range from 0.8 V to 3.6 V. This device is fully CC specified for partial power-down applications using I . The I circuitry disables the output, OFF OFF preventing the damaging backflow current through the device when it is powered down. This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications. 2. Features and benefits Automotive product qualification in accordance with AEC-Q100 (Grade 1) Specified from -40 C to +85 C and from -40 C to +125 C Wide supply voltage range from 0.8 V to 3.6 V CMOS low power dissipation High noise immunity Overvoltage tolerant inputs to 3.6 V Low noise overshoot and undershoot < 10 % of V CC I circuitry provides partial Power-down mode operation OFF Low static power consumption I = 0.9 A (maximum) CC Latch-up performance exceeds 100 mA per JESD 78 Class II Complies with JEDEC standards: JESD8-12 (0.8 V to 1.3 V) JESD8-11 (0.9 V to 1.65 V) JESD8-7 (1.65 V to 1.95 V) JESD8-5 (2.3 V to 2.7 V) JESD8C (2.7 V to 3.6 V) ESD protection: MIL-STD-883, method 3015 Class 3A. Exceeds 5000 V HBM JESD22-A114F Class 3A. Exceeds 5000 V MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 ) 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74AUP1G157GM-Q100 -40 C to +125 C XSON6 plastic extremely thin small outline package SOT886 no leads 6 terminals body 1 1.45 0.5 mmNexperia 74AUP1G157-Q100 Low-power 2-input multiplexer 4. Marking Table 2. Marking Type number Marking code 1 74AUP1G157GM-Q100 aP 1 The pin 1 indicator is located on the lower left corner of the device, below the marking code. 5. Functional diagram 1 3 6 G1 I1 I0 6 S 3 1 MUX 4 Y 1 1 4 001aac653 001aac652 Fig. 2. IEC logic symbol Fig. 1. Logic symbol S 1 I1 4 MULTIPLEXER SELECTOR Y 3 I1 OUTPUT S I0 Y 6 I0 001aac655 S 001aac654 Fig. 3. Functional diagram Fig. 4. Logic diagram 6. Pinning information 6.1. Pinning 74AUP1G157 I1 1 6 S GND 2 5 V CC I0 3 4 Y 001aae016 Transparent top view Fig. 5. Pin configuration SOT886 (XSON6) 74AUP1G157 Q100 All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2021. All rights reserved Product data sheet Rev. 2 4 November 2021 2 / 13