74AUP1T57GM,115 Nexperia

74AUP1T57 Low-power configurable gate with voltage-level translator Rev. 6 26 May 2021 Product data sheet 1. General description The 74AUP1T57 is a configurable multiple function gate with level translating, Schmitt-trigger inputs. The device can be configured as any of the following logic functions AND, OR, NAND, NOR, XNOR, inverter and buffer using the 3-bit input. All inputs can be connected directly to V CC or GND. Low threshold Schmitt trigger inputs allow these devices to be driven by 1.8 V logic levels in 3.3 V applications. This device ensures very low static and dynamic power consumption across the entire V range CC from 2.3 V to 3.6 V. This device is fully specified for partial power down applications using I . The OFF I circuitry disables the output, preventing the potentially damaging backflow current through the OFF device when it is powered down. 2. Features and benefits Wide supply voltage range from 2.3 V to 3.6 V High noise immunity Low static power consumption I = 1.5 A (maximum) CC Latch-up performance exceeds 100 mA per JESD 78 Class II Level B Overvoltage tolerant inputs to 3.6 V Low noise overshoot and undershoot < 10 % of V CC I circuitry provides partial power-down mode operation OFF ESD protection: HBM JESD22-A114F Class 3A exceeds 5000 V MM JESD22-A115-A exceeds 200 V CDM JESD22-C101E exceeds 1000 V Multiple package options Specified from -40 C to +85 C and -40 C to +125 C 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74AUP1T57GW -40 C to +125 C SC-88 plastic surface-mounted package 6 leads SOT363 74AUP1T57GM -40 C to +125 C XSON6 plastic extremely thin small outline package no leads SOT886 6 terminals body 1 1.45 0.5 mm 74AUP1T57GN -40 C to +125 C XSON6 extremely thin small outline package no leads SOT1115 6 terminals body 0.9 1.0 0.35 mm 74AUP1T57GS -40 C to +125 C XSON6 extremely thin small outline package no leads SOT1202 6 terminals body 1.0 1.0 0.35 mmNexperia 74AUP1T57 Low-power configurable gate with voltage-level translator 4. Marking Table 2. Marking Type number Marking code 1 74AUP1T57GW a7 74AUP1T57GM a7 74AUP1T57GN a7 74AUP1T57GS a7 1 The pin 1 indicator is located on the lower left corner of the device, below the marking code. 5. Functional diagram 3 A 4 Y 1 B 6 C 001aab583 Fig. 1. Logic symbol 6. Pinning information 6.1. Pinning 74AUP1T57 74AUP1T57 B 1 6 C 74AUP1T57 B 1 6 C B 1 6 C GND 2 5 V CC GND 2 5 V CC GND 2 5 V CC A 3 4 Y A 3 4 Y A 3 4 Y 001aah471 001aah473 001aah472 Transparent top view Transparent top view Fig. 2. Pin configuration Fig. 3. Pin configuration Fig. 4. Pin configuration SOT1115 SOT363 (SC-88) SOT886 (XSON6) and SOT1202 (XSON6) 74AUP1T57 All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2021. All rights reserved Product data sheet Rev. 6 26 May 2021 2 / 17