74AUP2GU04GM Nexperia

74AUP2GU04 Low-power dual unbuffered inverter Rev. 5 11 October 2013 Product data sheet 1. General description The 74AUP2GU04 provides two unbuffered inverting gates. This device ensures a very low static and dynamic power consumption across the entire V range from 0.8 V to 3.6 V. CC 2. Features and benefits Wide supply voltage range from 0.8 V to 3.6 V High noise immunity ESD protection: HBM JESD22-A114F Class 3A exceeds 5000 V MM JESD22-A115-A exceeds 200 V CDM JESD22-C101E exceeds 1000 V Low static power consumption I = 0.9 A (maximum) CC Latch-up performance exceeds 100 mA per JESD 78 Class II Inputs accept voltages up to 3.6 V Multiple package options Specified from 40 Cto+85 C and 40 Cto+125 C 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74AUP2GU04GW 40 C to +125 C SC-88 plastic surface-mounted package 6 leads SOT363 74AUP2GU04GM 40 C to +125 C XSON6 plastic extremely thin small outline package no leads SOT886 6 terminals body 1 1.45 0.5 mm 74AUP2GU04GF 40 C to +125 C XSON6 plastic extremely thin small outline package no leads SOT891 6 terminals body 1 1 0.5 mm 74AUP2GU04GN 40 C to +125 C XSON6 extremely thin small outline package no leads SOT1115 6 terminals body 0.9 1.0 0.35 mm 74AUP2GU04GS 40 C to +125 C XSON6 extremely thin small outline package no leads SOT1202 6 terminals body 1.0 1.0 0.35 mm74AUP2GU04 NXP Semiconductors Low-power dual unbuffered inverter 4. Marking Table 2. Marking 1 Type number Marking code 74AUP2GU04GW aD 74AUP2GU04GM aD 74AUP2GU04GF aD 74AUP2GU04GN aD 74AUP2GU04GS aD 1 The pin 1 indicator is located on the lower left corner of the device, below the marking code. 5. Functional diagram 1 1A 1Y 6 1 V CC 1 6 540 50 AY 1 3 2A 2Y 4 3 4 mnb106 mnb107 001aad073 Fig 1. Logic symbol Fig 2. IEC logic symbol Fig 3. Logic diagram (one gate) 6. Pinning information 6.1 Pinning 74AUP2GU04 74AUP2GU04 1A 1 6 1Y 74AUP2GU04 1A 1 6 1Y 1A 1 6 1Y GND 2 5 V CC GND 2 5 V CC GND 2 5 V CC 2A 3 4 2Y 2A 3 4 2Y 2A 3 4 2Y 001aad700 001aad701 Transparent top view Transparent top view 001aad699 Fig 4. Pin configuration SOT363 Fig 5. Pin configuration SOT886 Fig 6. Pin configuration SOT891, SOT1115 and SOT1202 74AUP2GU04 All information provided in this document is subject to legal disclaimers. NXP B.V. 2013. All rights reserved. Product data sheet Rev. 5 11 October 2013 2 of 19