74CBTLV3861PW,118 Nexperia

74CBTLV3861 10-bit bus switch with output enable Rev. 3 16 December 2011 Product data sheet 1. General description The 74CBTLV3861 is a 10-bit bus switch with one output enable (OE) input. When OE is LOW, the switch is closed and port A is connected to the B port. When OE is HIGH, the switch is disabled. To ensure the high-impedance OFF-state during power-up or power-down, OE should be tied to the V through a pull-up resistor. The minimum value of the resistor is determined CC by the current-sinking capability of the driver. Schmitt trigger action at control input makes the circuit tolerant to slower input rise and fall times across the entire V range from 2.3 V to 3.6 V. CC This device is fully specified for partial power-down applications using I . OFF The I circuitry disables the output, preventing the damaging backflow current through OFF the device when it is powered down. 2. Features and benefits Supply voltage range from 2.3 V to 3.6 V High noise immunity Complies with JEDEC standard: JESD8-5 (2.3 V to 2.7 V) JESD8-B/JESD36 (2.7 V to 3.6 V) ESD protection: HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V CDM AEC-Q100-011 revision B exceeds 1000 V 5 switch connection between two ports Rail to rail switching on data I/O ports CMOS low power consumption Latch-up performance exceeds 250 mA per JESD78B Class I level A I circuitry provides partial Power-down mode operation OFF Multiple package options Specified from 40 Cto+85 C and 40 Cto+125 C74CBTLV3861 NXP Semiconductors 10-bit bus switch with output enable 3. Ordering information Table 1. Ordering information Type number Package Temperature Name Description Version range 1 74CBTLV3861DK 40 C to +125 C SSOP24 plastic shrink small outline package 24 leads SOT556-1 body width 3.9 mm lead pitch 0.635 mm 74CBTLV3861PW 40 C to +125 C TSSOP24 plastic thin shrink small outline package 24 leads SOT355-1 body width 4.4 mm 74CBTLV3861BQ 40 C to +125 C DHVQFN24 plastic dual in-line compatible thermal enhanced very SOT815-1 thin quad flat package no leads 24 terminals body 3.5 5.5 0.85 mm 1 Also known as QSOP24 package 4. Functional diagram A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 2 3 4 5 6 7 8 9 10 11 23 OE 22 21 20 19 18 17 16 15 14 13 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 001aan142 Fig 1. Logic symbol nA nB OE 001aan143 Fig 2. Logic diagram (one switch) 74CBTLV3861 All information provided in this document is subject to legal disclaimers. NXP B.V. 2011. All rights reserved. Product data sheet Rev. 3 16 December 2011 2 of 18