74HC00-Q100 74HCT00-Q100 Quad 2-input NAND gate Rev. 5 22 October 2021 Product data sheet 1. General description The 74HC00-Q100 74HCT00-Q100 is a quad 2-input NAND gate. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of V . CC This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications. 2. Features and benefits Automotive product qualification in accordance with AEC-Q100 (Grade 1) Specified from -40 C to +85 C and from -40 C to +125 C Wide supply voltage range from 2.0 to 6.0 V CMOS low power dissipation High noise immunity Latch-up performance exceeds 100 mA per JESD 78 Class II Level B Input levels: For 74HC00-Q100: CMOS level For 74HCT00-Q100: TTL level Complies with JEDEC standards: JESD8C (2.7 V to 3.6 V) JESD7A (2.0 V to 6.0 V) ESD protection: MIL-STD-883, method 3015 exceeds 2000 V HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V (C = 200 pf, R = 0 ) Multiple package options DHVQFN package with Side-Wettable Flanks enabling Automatic Optical Inspection (AOI) of solder joints 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74HC00D-Q100 -40 C to +125 C SO14 plastic small outline package 14 leads SOT108-1 body width 3.9 mm 74HCT00D-Q100 74HC00PW-Q100 -40 C to +125 C TSSOP14 plastic thin shrink small outline package 14 leads SOT402-1 body width 4.4 mm 74HCT00PW-Q100 74HC00BQ-Q100 -40 C to +125 C DHVQFN14 plastic dual in-line compatible thermal SOT762-1 enhanced very thin quad flat package no leads 74HCT00BQ-Q100 14 terminals body 2.5 3 0.85 mmNexperia 74HC00-Q100 74HCT00-Q100 Quad 2-input NAND gate 4. Functional diagram 1 3 & 1 1A 2 1Y 3 2 1B 4 4 2A 6 & 2Y 6 5 5 2B 9 9 3A 3Y 8 8 & 10 3B 10 A 12 4A 12 4Y 11 Y 11 13 4B & 13 B mna212 mna246 mna211 Fig. 1. Logic symbol Fig. 2. IEC logic symbol Fig. 3. Logic diagram (one gate) 5. Pinning information 5.1. Pinning 74HC00 74HCT00 terminal 1 index area 1B 2 13 4B 74HC00 74HCT00 3 12 1Y 4A 2A 4 11 4Y 1A 1 14 V CC 2B 5 10 3B (1) GND 1B 2 13 4B 2Y 6 9 3A 1Y 3 12 4A 2A 4 11 4Y 001aal324 2B 5 10 3B 2Y 6 9 3A Transparent top view GND 7 8 3Y (1) This is not a ground pin. There is no electrical or mechanical requirement to solder the pad. In case 001aal323 soldered, the solder land should remain floating or connected to GND. Fig. 4. Pin configuration SOT108-1 (SO14) and SOT402-1 (TSSOP14) Fig. 5. Pin configuration SOT762-1 (DHVQFN14) 5.2. Pin description Table 2. Pin description Symbol Pin Description 1A, 2A, 3A, 4A 1, 4, 9, 12 data input 1B, 2B, 3B, 4B 2, 5, 10, 13 data input 1Y, 2Y, 3Y, 4Y 3, 6, 8, 11 data output GND 7 ground (0 V) V 14 supply voltage CC 74HC HCT00 Q100 All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2021. All rights reserved Product data sheet Rev. 5 22 October 2021 2 / 12 GND 7 1 1A 3Y 8 14 V CC