74HC161D-Q100J Nexperia

74HC161-Q100 Presettable synchronous 4-bit binary counter asynchronous reset Rev. 3 16 March 2021 Product data sheet 1. General description The 74HC161-Q100 is a synchronous presettable binary counter with an internal look-head carry. Synchronous operation is provided by having all flip-flops clocked simultaneously on the positive- going edge of the clock (CP). The outputs (Q0 to Q3) of the counters may be preset HIGH or LOW. A LOW at the parallel enable input (PE) disables the counting action and causes the data at the data inputs (D0 to D3) to be loaded into the counter on the positive-going edge of the clock. Preset takes place regardless of the levels at count enable inputs (CEP and CET). A LOW at the master reset input (MR) sets Q0 to Q3 LOW regardless of the levels at input pins CP, PE, CET and CEP (thus providing an asynchronous clear function). The look-ahead carry simplifies serial cascading of the counters. Both CEP and CET must be HIGH to count. The CET input is fed forward to enable the terminal count output (TC). The TC output thus enabled will produce a HIGH output pulse of a duration approximately equal to a HIGH output of Q0. This pulse can be used to enable the next cascaded stage. The maximum clock frequency for the cascaded counters is determined by the CP to TC propagation delay and CEP to CP set-up time, according to the following formula: Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of V . CC This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications. 2. Features and benefits Automotive product qualification in accordance with AEC-Q100 (Grade 1) Specified from -40 C to +85 C and from -40 C to +125 C Wide supply voltage range from 2.0 V to 6.0 V CMOS low power dissipation High noise immunity Latch-up performance exceeds 100 mA per JESD 78 Class II Level B Complies with JEDEC standards: JESD8C (2.7 V to 3.6 V) JESD7A (2.0 V to 6.0 V) CMOS input levels Synchronous counting and loading 2 count enable inputs for n-bit cascading Asynchronous reset Positive-edge triggered clock ESD protection: MIL-STD-883, method 3015 exceeds 2000 V HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 )Nexperia 74HC161-Q100 Presettable synchronous 4-bit binary counter asynchronous reset 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74HC161D-Q100 -40 C to +125 C SO16 plastic small outline package 16 leads SOT109-1 body width 3.9 mm 74HC161PW-Q100 -40 C to +125 C TSSOP16 plastic thin shrink small outline package 16 leads SOT403-1 body width 4.4 mm 4. Functional diagram 1 CTR4 R 9 M1 15 7 G3 10 TC G4 2 3 D0 Q0 14 C2/1,3,4+ 4 D1 Q1 13 14 3 1,2D 5 D2 Q2 12 4 13 6 D3 Q3 11 5 12 9 PE 6 11 CEP CET CP MR 15 4 CT = 15 7 10 2 1 mna905 mna906 Fig. 1. Logic symbol Fig. 2. IEC logic symbol 3 4 5 6 D0 D1 D2 D3 PE PARALLEL LOAD 9 CIRCUITRY CET 10 TC 15 CEP 7 BINARY CP 2 COUNTER MR 1 Q0 Q1 Q2 Q3 mna907 14 13 12 11 Fig. 3. Functional diagram 74HC161 Q100 All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2021. All rights reserved Product data sheet Rev. 3 16 March 2021 2 / 17