74HC1G32GW-Q100H Nexperia

74HC1G32-Q100 74HCT1G32-Q100 2-input OR gate Rev. 1 8 August 2012 Product data sheet 1. General description 74HC1G32-Q100 and 74HCT1G32-Q100 are high-speed Si-gate CMOS devices. They provide a 2-input OR function. The standard output currents are half of those of the 74HC32-Q100 and 74HCT32-Q100. This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications. 2. Features and benefits Automotive product qualification in accordance with AEC-Q100 (Grade 1) Specified from 40 C to +85 C and from 40 C to +125 C Input levels: For 74HC1G32-Q100: CMOS level For 74HCT1G32-Q100: TTL level Symmetrical output impedance High noise immunity Low power dissipation Balanced propagation delays ESD protection: MIL-STD-883, method 3015 exceeds 2000 V HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 ) SOT353-1 and SOT753 package options 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74HC1G32GW-Q100 40 C to +125 C TSSOP5 plastic thin shrink small outline package 5 leads SOT353-1 body width 1.25 mm 74HCT1G32GW-Q100 74HC1G32GV-Q100 40 C to +125 C SC-74A plastic surface-mounted package 5 leads SOT753 74HCT1G32GV-Q100Nexperia 74HC1G32-Q100 74HCT1G32-Q100 2-input OR gate 4. Marking Table 2. Marking codes 1 Type number Marking code 74HC1G32GW-Q100 HG 74HCT1G32GW-Q100 TG 74HC1G32GV-Q100 H32 74HCT1G32GV-Q100 T32 1 The pin 1 indicator is located on the lower left corner of the device, below the marking code. 5. Functional diagram 1 1 B 1 Y 4 4 2 A 2 mna164 mna165 Fig 1. Logic symbol Fig 2. IEC logic symbol B Y A mna166 Fig 3. Logic diagram 6. Pinning information 6.1 Pinning Fig 4. Pin configuration 74HC HCT1G32 Q100 All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2017. All rights reserved Product data sheet Rev. 1 8 August 2012 2 of 12