INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT221
Dual non-retriggerable monostable
multivibrator with reset
December 1990
Product specication
Supersedes data of April 1988
File under Integrated Circuits, IC06Philips Semiconductors Product specication
Dual non-retriggerable monostable
74HC/HCT221
multivibrator with reset
FEATURES jitter-free triggering from inputs with slow transition rates,
providing the circuit with excellent noise immunity.
Pulse width variance is typically less than 5%
Once triggered, the outputs (nQ, nQ) are independent of
Pin-out identical to 123
further transitions of nA and nB inputs and are a function
Overriding reset terminates output pulse
of the timing components. The output pulses can be
nB inputs have hysteresis for improved noise immunity terminated by the overriding active LOW reset inputs
(nR ). Input pulses may be of any duration relative to the
D
Output capability: standard (except for nR /C )
EXT EXT
output pulse.
I category: MSI
CC
Pulse width stability is achieved through internal
compensation and is virtually independent of V and
CC
GENERAL DESCRIPTION
temperature. In most applications pulse stability will only
be limited by the accuracy of the external timing
The 74HC/HCT221 are high-speed Si-gate CMOS devices
components.
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
The output pulse width is defined by the following
standard no. 7A.
relationship:
The 74HC/HCT221 are dual non-retriggerable monostable
t =C R In
W EXT EXT 2
multivibrators. Each multivibrator features an active
t = 0.7C R
W EXT EXT
LOW-going edge input (nA) and an active HIGH-going
Pin assignments for the 221 are identical to those of the
edge input (nB), either of which can be used as an enable
123 so that the 221 can be substituted for those
input.
products in systems not using the retrigger by merely
Pulse triggering occurs at a particular voltage level and is
changing the value of R and/or C .
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not directly related to the transition time of the input pulse.
Schmitt-trigger input circuitry for the nB inputs allow
QUICK REFERENCE DATA
GND = 0 V; T =25C; t =t = 6 ns
amb r f
TYPICAL
SYMBOL PARAMETER CONDITIONS UNIT
HC HCT
propagation delay C = 15 pF; V =5 V;
L CC
R =5 k; C = 0 pF
EXT EXT
t nA, nB, nR to nQ, nQ 2932ns
PHL D
t nA, nB, nR to nQ, nQ 3536ns
PLH D
C input capacitance 3.5 3.5 pF
I
C power dissipation capacitance per package notes 1 and 2 90 96 pF
PD
Notes
1. C is used to determine the dynamic power dissipation (P in W):
PD D
2 2 2
P =C V f + (C V f ) + 0.33 C V f + D 28 V where:
D PD CC i L CC o EXT CC o CC
f = input frequency in MHz; f = output frequency in MHz
i o
2
(C V f ) = sum of outputs
L CC o
C = timing capacitance in pF; C = output load capacitance in pF
EXT L
V = supply voltage in V; D = duty factor in %
CC
2. For HC the condition is V = GND to V
I CC
For HCT the condition is V = GND to V - 1.5 V
I CC
December 1990 2