74HC259D Nexperia

74HC259 74HCT259 8-bit addressable latch Rev. 5 7 August 2012 Product data sheet 1. General description The 74HC259 74HCT259 are high-speed Si-gate CMOS devices and are pin compatible with Low-power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard No. 7-A. The 74HC259 74HCT259 are high-speed 8-bit addressable latches designed for general-purpose storage applications in digital systems. They are multifunctional devices capable of storing single-line data in eight addressable latches. They provide a 3-to-8 decoder and multiplexer function with active HIGH outputs (Q0 to Q7). They also incorporate an active LOW common reset (MR) for resetting all latches as well as an active LOW enable input (LE). The 74HC259 74HCT259 has four modes of operation: Addressable latch mode, in this mode data on the data line (D) is written into the addressed latch. The addressed latch follows the data input with all non-addressed latches remaining in their previous states. Memory mode, in this mode all latches remain in their previous states and are unaffected by the data or address inputs. Demultiplexing mode (or 3-to-8 decoding), in this mode the addressed output follows the state of the data input (D) with all other outputs in the LOW state. Reset mode, in this mode all outputs are LOW and unaffected by the address inputs (A0 to A2) and data input (D). When operating the 74HC259 74HCT259 as an address latch, changing more than one address bit could impose a transient wrong address. Therefore, this should only be done while in the Memory mode. 2. Features and benefits Combined demultiplexer and 8-bit latch Serial-to-parallel capability Output from each storage bit available Random (addressable) data entry Easily expandable Common reset input Useful as a 3-to-8 active HIGH decoder Input levels: For 74HC259: CMOS level For 74HCT259: TTL level74HC259 74HCT259 NXP Semiconductors 8-bit addressable latch ESD protection: HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V CDM JESD22E exceeds 1000 V Multiple package options Specified from 40 C to +85 C and from 40 C to +125 C 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74HC259N 40 C to +125 C DIP16 plastic dual in-line package 16 leads (300 mil) SOT38-4 74HCT259N 74HC259D 40 C to +125 C SO16 plastic small outline package 16 leads SOT109-1 body width 3.9 mm 74HCT259D 74HC259DB 40 C to +125 C SSOP16 plastic shrink small outline package 16 leads body SOT338-1 width 5.3 mm 74HCT259DB 74HC259PW 40 C to +125 C TSSOP16 plastic thin shrink small outline package 16 leads SOT403-1 body width 4.4 mm 74HCT259PW 74HC259BQ 40 C to +125 C DHVQFN16 plastic dual in-line compatible thermal enhanced very SOT763-1 thin quad flat package no leads 16 terminals 74HCT259BQ body 2.5 3.5 0.85 mm 4. Functional diagram 13 Z9 15 G8 14 G10 9,10D DX 4 14 C10 1 0 8R 1 LE 0 5 2 4 0 Q0 G 1 7 3 13 5 6 2 D Q1 2 6 7 Q2 7 3 Q3 9 1 9 A0 4 Q4 2 10 10 A1 Q5 5 3 11 A2 Q6 11 12 6 Q7 12 MR 7 15 mna573 mna572 Fig 1. Logic symbol Fig 2. IEC logic symbol 74HC HCT259 All information provided in this document is subject to legal disclaimers. NXP B.V. 2012. All rights reserved. Product data sheet Rev. 5 7 August 2012 2 of 22