74HC42D Nexperia

INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications The IC06 74HC/HCT/HCU/HCMOS Logic Package Information The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines 74HC/HCT42 BCD to decimal decoder (1-of-10) December 1990 Product specication File under Integrated Circuits, IC06Philips Semiconductors Product specication BCD to decimal decoder (1-of-10) 74HC/HCT42 FEATURES The 74HC/HCT42 decoders accept four active HIGH BCD inputs and provide 10 mutually exclusive active LOW Mutually exclusive outputs outputs. The active LOW outputs facilitate addressing 1-of-8 demultiplexing capability other MSI circuits with active LOW input enables. Outputs disabled for input codes above nine The logic design of the 42 ensures that all outputs are Output capability: standard HIGH when binary codes greater than nine are applied to the inputs. I category: MSI CC The most significant input (A ) produces an useful inhibit 3 function when the 42 is used as a 1-of-8 decoder. The A 3 GENERAL DESCRIPTION input can also be used as the data input in an 8-output The 74HC/HCT42 are high-speed Si-gate CMOS devices demultiplexer application. and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. QUICK REFERENCE DATA GND = 0 V T =25 C t =t = 6 ns amb r f TYPICAL SYMBOL PARAMETER CONDITIONS UNIT HC HCT t / t propagation delay A to Y C = 15 pF V = 5 V 14 17 ns PHL PLH n n L CC C input capacitance 3.5 3.5 pF I C power dissipation capacitance per package notes 1 and 2 37 37 pF PD Notes 1. C is used to determine the dynamic power dissipation (P in W): PD D 2 2 P =C V f + (C V f ) where: D PD CC i L CC o f = input frequency in MHz i f = output frequency in MHz o 2 (C V f ) = sum of outputs L CC o C = output load capacitance in pF L V = supply voltage in V CC 2. For HC the condition is V = GND to V I CC For HCT the condition is V = GND to V - 1.5 V I CC ORDERING INFORMATION See 74HC/HCT/HCU/HCMOS Logic Package Information. December 1990 2