74HCT02D Nexperia

74HC02 74HCT02 Quad 2-input NOR gate Rev. 5 26 November 2015 Product data sheet 1. General description The 74HC02 74HCT02 is a quad 2-input NOR gate. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of V . CC 2. Features and benefits Input levels: For 74HC02: CMOS level For 74HCT02: TTL level Complies with JEDEC standard no. 7A ESD protection: HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V Multiple package options Specified from 40 C to +85 C and from 40 C to +125 C 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74HC02D 40 C to +125 C SO14 plastic small outline package 14 leads body width SOT108-1 3.9 mm 74HCT02D 74HC02DB 40 C to +125 C SSOP14 plastic shrink small outline package 14 leads body SOT337-1 width 5.3 mm 74HCT02DB 74HC02PW 40 C to +125 C TSSOP14 plastic thin shrink small outline package 14 leads SOT402-1 body width 4.4 mm 74HCT02PW 74HC02BQ 40 C to +125 C DHVQFN14 plastic dual in-line compatible thermal enhanced very SOT762-1 thin quad flat package no leads 14 terminals 74HCT02BQ body 2.5 3 0.85 mm&& *1 74HC02 74HCT02 NXP Semiconductors Quad 2-input NOR gate 4. Functional diagram < % < % < % < < % % D PQ PQ D Fig 1. Logic symbol Fig 2. IEC logic symbol Fig 3. Logic diagram (one gate) 5. Pinning information 5.1 Pinning WHUPDO LQ 9 QGH DUHDL 9 WYR HL U 7 (1) This is not a supply pin. The substrate is attached to this pad using conductive die attach material. There is no electrical or mechanical requirement to solder this pad. However, if it is soldered, the solder land should remain floating or be connected to GND. Fig 4. Pin configuration SO14 and (T)SSOP14 Fig 5. Pin configuration DHVQFN14 5.2 Pin description Table 2. Pin description Symbol Pin Description 1Y to 4Y 1, 4, 10, 13 data output 1A to 4A 2, 5, 8, 11 data input 1B to 4B 3, 6, 9,12 data input GND 7 ground (0 V) V 14 supply voltage CC 74HC HCT02 All information provided in this document is subject to legal disclaimers. NXP Semiconductors N.V. 2015. All rights reserved. Product data sheet Rev. 5 26 November 2015 2 of 15 < DQVSDUQW S HZ DDF *1 DDF % % < % % < *1 < % % < < && < % % < DDK