74HCT112D Nexperia

INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications The IC06 74HC/HCT/HCU/HCMOS Logic Package Information The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines 74HC/HCT112 Dual JK flip-flop with set and reset negative-edge trigger 1998 Jun 10 Product specication Supersedes data of December 1990 File under Integrated Circuits, IC06Philips Semiconductors Product specication Dual JK ip-op with set and reset 74HC/HCT112 negative-edge trigger FEATURES The set and reset inputs, when LOW, set or reset the outputs as shown in the function table regardless of the Asynchronous set and reset levels at the other inputs. Output capability: standard A HIGH level at the clock (nCP) input enables the nJ and I category: flip-flops CC nK inputs and data will be accepted. The nJ and nK inputs control the state changes of the flip-flops as shown in the function table. The nJ and nK inputs must be stable one GENERAL DESCRIPTION set-up time prior to the HIGH-to-LOW clock transition for The 74HC/HCT112 are high-speed Si-gate CMOS devices predictable operation. and are pin compatible with low power Schottky TTL Output state changes are initiated by the HIGH-to-LOW (LSTTL). They are specified in compliance with JEDEC transition of nCP. standard no. 7A. Schmitt-trigger action in the clock input makes the circuit The 74HC/HCT112 are dual negative-edge triggered highly tolerant to slower clock rise and fall times. JK-type flip-flops featuring individual nJ, nK, clock (nCP), set (nS ) and reset (nR ) inputs. D D QUICK REFERENCE DATA GND = 0 V T =25C t =t = 6 ns amb r f TYPICAL SYMBOL PARAMETER CONDITIONS UNIT HC HCT t / t propagation delay C = 15 pF V =5 V PHL PLH L CC nCP to nQ, nQ 1719ns nS to nQ, nQ 1515ns D nR to nQ, nQ 1819ns D f maximum clock frequency 66 70 MHz max C input capacitance 3.5 3.5 pF I C power dissipation capacitance per ip-op notes 1 and 2 27 30 pF PD Notes 1. C is used to determine the dynamic power dissipation (P in W): PD D 2 2 P =C V f + (C V f ) where: D PD CC i L CC o f = input frequency in MHz i f = output frequency in MHz o 2 (C V f ) = sum of outputs L CC o C = output load capacitance in pF L V = supply voltage in V CC 2. For HC the condition is V = GND to V I CC For HCT the condition is V = GND to V - 1.5 V I CC 1998 Jun 10 2