74HCT138PW Nexperia

74HC138; 74HCT138 3-to-8 line decoder/demultiplexer; inverting Rev. 4 27 June 2012 Product data sheet 1. General description The 74HC138; 74HCT138 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). The 74HC138; 74HCT138 decoder accepts three binary weighted address inputs (A0, A1 and A3) and when enabled, provides 8 mutually exclusive active LOW outputs (Y0to Y7). The 74HC138; 74HCT138 features three enable inputs: two active LOW (E1 and E2) and one active HIGH (E3). Every output is HIGH unless E1 and E2 are LOW and E3 is HIGH. This multiple enable function allows easy parallel expansion of the 74HC138; 74HCT138 to a 1-of-32 (5 lines to 32 lines) decoder with just four 74HC138; 74HCT138 ICs and one inverter. The 74HC138; 74HCT138 can be used as an eight output demultiplexer by using one of the active LOW enable inputs as the data input and the remaining enable inputs as strobes. Permanently tie unused enable inputs to their appropriate active HIGH- or LOW-state. The 74HC138; 74HCT138 is identical to the 74HC238; 74HCT238 but has inverting outputs. 2. Features and benefits Demultiplexing capability Multiple input enable for easy expansion Complies with JEDEC standard no. 7A Ideal for memory chip select decoding Active LOW mutually exclusive outputs ESD protection: HBM EIA/JESD22-A114F exceeds 2000 V MM EIA/JESD22-A115-A exceeds 200 V Multiple package options Specified from 40 Cto+85 C and from 40 Cto+125 C74HC138; 74HCT138 NXP Semiconductors 3-to-8 line decoder/demultiplexer; inverting 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74HC138N 40 Cto+125 C DIP16 plastic dual in-line package; 16 leads (300 mil) SOT38-4 74HCT138N 74HC138D 40 Cto+125 C SO16 plastic small outline package; 16 leads; SOT109-1 body width 3.9 mm 74 HCT138D 74HC138DB 40 Cto+125 C SSOP16 plastic shrink small outline package; 16 leads; SOT338-1 body width 5.3 mm 74HCT138DB 74HC138PW 40 Cto+125 C TSSOP16 plastic thin shrink small outline package; SOT403-1 16 leads; body width 4.4 mm 74HCT138PW 74HC138BQ 40 Cto+125 C DHVQFN16 plastic dual in-line compatible thermal enhanced SOT763-1 very thin quad flat package; no leads; 74HCT138BQ 16 terminals; body 2.5 3.5 0.85 mm 4. Functional diagram Y0 15 1 A0 Y1 14 Y0 1 A0 15 2 A1 13 Y2 2 A1 Y1 14 A2 3 Y3 12 3-to-8 ENABLE 13 3 A2 Y2 Y4 11 DECODER EXITING 12 Y3 Y5 10 E1 Y4 11 Y6 9 4 Y5 10 E2 Y7 7 5 9 Y6 E3 6 4 E1 Y7 7 5 E2 mna370 6 E3 mna372 Fig 1. Logic symbol Fig 2. Functional diagram 74HC_HCT138 All information provided in this document is subject to legal disclaimers. NXP B.V. 2012. All rights reserved. Product data sheet Rev. 4 27 June 2012 2 of 19