74HCT20N Nexperia

74HC20 74HCT20 Dual 4-input NAND gate Rev. 3 3 September 2012 Product data sheet 1. General description The 74HC20 74HCT20 is a dual 4-input NAND gate. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of V . CC 2. Features and benefits Complies with JEDEC standard JESD7A Low-power dissipation Input levels: For 74HC20: CMOS level For 74HCT20: TTL level ESD protection: HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V Multiple package options Specified from 40 Cto+80 C and from 40 Cto+125 C. 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74HC20N 40 C to +125 C DIP14 plastic dual in-line package 14 leads (300 mil) SOT27-1 74HCT20N 74HC20D 40 C to +125 C SO14 plastic small outline package 14 leads body width SOT108-1 3.9 mm 74HCT20D 74HC20DB 40 C to +125 C SSOP14 plastic shrink small outline package 14 leads body SOT337-1 width 5.3 mm 74HCT20DB 74HC20PW 40 C to +125 C TSSOP14 plastic thin shrink small outline package 14 leads SOT402-1 body width 4.4 mm 74HCT20PW74HC20 74HCT20 NXP Semiconductors Dual 4-input NAND gate 4. Functional diagram Fig 1. Functional diagram Fig 2. Logic symbol Fig 3. IEC Logic symbol Fig 4. Logic diagram 5. Pinning information 5.1 Pinning Fig 5. Pin configuration SOT27-1 and SOT108-1 Fig 6. Pin configuration SOT337-1 and SOT402-1 74HC HCT20 All information provided in this document is subject to legal disclaimers. NXP B.V. 2012. All rights reserved. Product data sheet Rev. 3 3 September 2012 2 of 16