74LVC10APW,112 Nexperia

74LVC10A Triple 3-input NAND gate Rev. 6 15 April 2021 Product data sheet 1. General description The 74LVC10A provides three 3-input NAND functions. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V applications. 2. Features and benefits Wide supply voltage range from 1.2 V to 3.6 V Inputs accept voltages up to 5.5 V CMOS low power consumption Direct interface with TTL levels Latch-up performance exceeds 250 mA Complies with JEDEC standard: JESD8-7A (1.65 V to 1.95 V) JESD8-5A (2.3 V to 2.7 V) JESD8-C/JESD36 (2.7 V to 3.6 V) ESD protection: HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-B exceeds 200 V CDM JESD22-C101E exceeds 1000 V Specified from -40 C to +85 C and -40 C to +125 C 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74LVC10AD -40 C to +125 C SO14 plastic small outline package 14 leads SOT108-1 body width 3.9 mm 74LVC10APW -40 C to +125 C TSSOP14 plastic thin shrink small outline package 14 leads SOT402-1 body width 4.4 mm 74LVC10ABQ -40 C to +125 C DHVQFN14 plastic dual in-line compatible thermal enhanced SOT762-1 very thin quad flat package no leads 14 terminals body 2.5 3 0.85 mmNexperia 74LVC10A Triple 3-input NAND gate 4. Functional diagram 1 & 12 2 1 1A 1Y 13 12 2 1B 13 1C 3 3 2A & 6 4 2Y 4 2B 6 5 5 2C A 9 3A 9 3Y 8 10 3B & Y B 10 8 11 3C 11 C mna758 mna757 mna759 Fig. 1. Logic symbol Fig. 2. IEC logic symbol Fig. 3. Logic diagram (one gate) 5. Pinning information 5.1. Pinning 74LVC10A terminal 1 index area 74LVC10A 2 13 1B 1C 2A 3 12 1Y 1A 1 14 V CC 2B 4 11 3C 1B 2 13 1C 2C 5 10 3B (1) GND 2A 3 12 1Y 2Y 6 9 3A 2B 4 11 3C 2C 5 10 3B 001aad048 Transparent top view 2Y 6 9 3A (1) This is not a ground pin. There is no electrical or GND 7 8 3Y mechanical requirement to solder the pad. In case 001aad047 soldered, the solder land should remain floating or connected to GND. Fig. 4. Pin configuration SOT108-1 (SO14) and SOT402-1 (TSSOP14) Fig. 5. Pin configuration SOT762-1 (DHVQFN14) 5.2. Pin description Table 2. Pin description Symbol Pin Description 1A, 2A, 3A 1, 3, 9 data input 1B, 2B, 3B 2, 4, 10 data input 1C, 2C, 3C 13, 5, 11 data input 1Y, 2Y, 3Y 12, 6, 8 data output GND 7 ground (0 V) V 14 supply voltage CC 74LVC10A All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2021. All rights reserved Product data sheet Rev. 6 15 April 2021 2 / 12 GND 7 1 1A 3Y 8 14 V CC