74LVC2G02DC-Q100H Nexperia

74LVC2G02-Q100 Dual 2-input NOR gate Rev. 3 21 July 2021 Product data sheet 1. General description The 74LVC2G02-Q100 is a dual 2-input NOR gate. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments. Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times. This device is fully specified for partial power down applications using I . The I circuitry OFF OFF disables the output, preventing the potentially damaging backflow current through the device when it is powered down. This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications. 2. Features and benefits Automotive product qualification in accordance with AEC-Q100 (Grade 1) Specified from -40 C to +85 C and from -40 C to +125 C Wide supply voltage range from 1.65 V to 5.5 V 5 V tolerant outputs for interfacing with 5 V logic Overvoltage tolerant inputs to 5.5 V High noise immunity 24 mA output drive (V = 3.0 V) CC CMOS low power consumption I circuitry provides partial Power-down mode operation OFF Latch-up performance exceeds 250 mA Direct interface with TTL levels Complies with JEDEC standard: JESD8-7 (1.65 V to 1.95 V) JESD8-5 (2.3 V to 2.7 V) JESD8-B/JESD36 (2.7 V to 3.6 V) ESD protection: MIL-STD-883, method 3015 exceeds 2000 V HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 ) 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74LVC2G02DP-Q100 -40 C to +125 C TSSOP8 plastic thin shrink small outline package SOT505-2 8 leads body width 3 mm lead length 0.5 mm 74LVC2G02DC-Q100 -40 C to +125 C VSSOP8 plastic very thin shrink small outline package SOT765-1 8 leads body width 2.3 mmNexperia 74LVC2G02-Q100 Dual 2-input NOR gate 4. Marking Table 2. Marking codes Type number Marking code 1 74LVC2G02DP-Q100 V02 74LVC2G02DC-Q100 V02 1 The pin 1 indicator is located on the lower left corner of the device, below the marking code. 5. Functional diagram 1 1A 1Y 1B B 2A 1 2Y Y 2B A 001aah780 mna105 001aah781 Fig. 1. Logic symbol Fig. 2. IEC logic symbol Fig. 3. Logic diagram (one gate) 6. Pinning information 6.1. Pinning 74LVC2G02 1A 1 8 V CC 1B 2 7 1Y 3 6 2Y 2B 4 5 GND 2A 001aab642 Fig. 4. Pin configuration SOT505-2 (TSSOP8) and SOT765-1 (VSSOP8) 6.2. Pin description Table 3. Pin description Symbol Pin Description 1A, 2A 1, 5 data input 1B, 2B 2, 6 data input GND 4 ground (0 V) 1Y, 2Y 7, 3 data output V 8 supply voltage CC 74LVC2G02 Q100 All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2021. All rights reserved Product data sheet Rev. 3 21 July 2021 2 / 12