74LVC2G08DP-Q100H Nexperia

74LVC2G08-Q100 Dual 2-input AND gate Rev. 3 28 January 2019 Product data sheet 1. General description The 74LVC2G08-Q100 provides a 2-input AND gate function. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of the 74LVC2G08-Q100 as a translator in a mixed 3.3 V and 5 V environment. This device is fully specified for partial power-down applications using I . The I circuitry OFF OFF disables the output, preventing a damaging backflow current through the device when it is powered down. This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications. 2. Features and benefits Automotive product qualification in accordance with AEC-Q100 (Grade 1) Specified from -40 C to +85 C and from -40 C to +125 C Wide supply voltage range from 1.65 V to 5.5 V 5 V tolerant outputs for interfacing with 5 V logic High noise immunity 24 mA output drive (V = 3.0 V) CC CMOS low power consumption Complies with JEDEC standard: JESD8-7 (1.65 V to 1.95 V) JESD8-5 (2.3 V to 2.7 V) JESD8-B/JESD36 (2.7 V to 3.6 V) Latch-up performance exceeds 250 mA Direct interface with TTL levels Inputs accept voltages up to 5 V ESD protection: MIL-STD-883, method 3015 exceeds 2000 V HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 ) Multiple package options 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74LVC2G08DP-Q100 -40 C to +125 C TSSOP8 plastic thin shrink small outline package 8 leads SOT505-2 body width 3 mm lead length 0.5 mm 74LVC2G08DC-Q100 -40 C to +125 C VSSOP8 plastic very thin shrink small outline package SOT765-1 8 leads body width 2.3 mm 74LVC2G08GS-Q100 -40 C to +125 C XSON8 extremely thin small outline package no leads SOT1203 8 terminals body 1.35 x 1.0 x 0.35 mmNexperia 74LVC2G08-Q100 Dual 2-input AND gate 4. Marking Table 2. Marking codes Type number Marking code 1 74LVC2G08DP-Q100 V08 74LVC2G08DC-Q100 V08 74LVC2G08GS-Q100 VE 1 The pin 1 indicator is located on the lower left corner of the device, below the marking code. 5. Functional diagram & 1A 1Y 1B A 2A 2Y & Y 2B B 001aah788 001aah789 mna221 Fig. 1. Logic symbol Fig. 2. IEC logic symbol Fig. 3. Logic diagram (one gate) 6. Pinning information 6.1. Pinning 74LVC2G08 1A 1 8 V CC 74LVC2G08 1B 2 7 1Y 1A 1 8 V CC 2Y 3 6 2B 1B 2 7 1Y 2Y 3 6 2B GND 4 5 2A GND 4 5 2A 001aae982 001aae981 Transparent top view Fig. 4. Pin configuration SOT505-2 (TSSOP8) and SOT765-1 (VSSOP8) Fig. 5. Pin configuration SOT1203 (XSON8) 74LVC2G08 Q100 All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2019. All rights reserved Product data sheet Rev. 3 28 January 2019 2 / 13