74LVC32APW-Q100J Nexperia

74LVC32A-Q100 Quad 2-input OR gate Rev. 4 27 May 2020 Product data sheet 1. General description The 74LVC32A-Q100 is a quad 2-input OR gate. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments. Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times. This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications. 2. Features and benefits Automotive product qualification in accordance with AEC-Q100 (Grade 1) Specified from -40 C to +85 C and from -40 C to +125 C Wide supply voltage range from 1.2 V to 3.6 V Overvoltage tolerant inputs to 5.5 V CMOS low power dissipation Direct interface with TTL levels Complies with JEDEC standard: JESD8-7A (1.65 V to 1.95 V) JESD8-5A (2.3 V to 2.7 V) JESD8-C/JESD36 (2.7 V to 3.6 V) ESD protection: MIL-STD-883, method 3015 exceeds 2000 V HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 ) Multiple package options DHVQFN package with Side-Wettable Flanks enabling Automatic Optical Inspection (AOI) of solder joints 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74LVC32AD-Q100 -40 C to +125 C SO14 plastic small outline package 14 leads SOT108-1 body width 3.9 mm 74LVC32APW-Q100 -40 C to +125 C TSSOP14 plastic thin shrink small outline package 14 leads SOT402-1 body width 4.4 mm 74LVC32ABQ-Q100 -40 C to +125 C DHVQFN14 plastic dual in-line compatible thermal SOT762-1 enhanced very thin quad flat package no leads 14 terminals body 2.5 3 0.85 mmNexperia 74LVC32A-Q100 Quad 2-input OR gate 4. Functional diagram 1 1 3 2 4 1 6 1 1A 1Y 3 5 2 1B 4 2A 2Y 6 9 5 2B 1 8 10 9 3A 3Y 8 10 3B 12 12 4A 1 4Y 11 11 13 4B 13 mna242 mna243 Fig. 1. Logic symbol Fig. 2. IEC logic symbol A Y B mna241 Fig. 3. Logic diagram for one gate 5. Pinning information 5.1. Pinning 74LVC32A-Q100 1 14 1A V CC 74LVC32A-Q100 1B 2 13 4B 1A 1 14 V 3 12 CC 1Y 4A 1B 2 13 4B 2A 4 11 4Y 1Y 3 12 4A 2A 4 11 4Y 2B 5 10 3B 2B 5 10 3B 2Y 6 9 3A 2Y 6 9 3A GND 7 8 3Y GND 7 8 3Y aaa-003859 aaa-028970 Fig. 4. Pin configuration SOT108-1 (SO14) Fig. 5. Pin configuration SOT402-1 (TSSOP14) 74LVC32A Q100 All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2020. All rights reserved Product data sheet Rev. 4 27 May 2020 2 / 13