74VHC14PW,118 Nexperia

74VHC14 74VHCT14 Hex inverting Schmitt trigger Rev. 01 17 August 2009 Product data sheet 1. General description The 74VHC14 74VHCT14 are a high-speed Si-gate CMOS devices and are pin compatible with Low-power Schottky TTL (LSTTL). They are specied in compliance with JEDEC standard No. 7A. The 74VHC14 74VHCT14 provide six inverting buffers with Schmitt-trigger action. They are capable of transforming slowly changing input signals into sharply dened, jitter-free output signals. 2. Features n Balanced propagation delays n All inputs have Schmitt-trigger action n Inputs accept voltages higher than V CC n Input levels: u The 74VHC14 operates with CMOS input level u The 74VHCT14 operates with TTL input level n ESD protection: u HBM EIA/JESD22-A114E exceeds 2000 V u MM EIA/JESD22-A115-A exceeds 200 V u CDM EIA/JESD22-C101C exceeds 1000 V n Multiple package options n Specied from 40- C to +85 C and from 40- C to +125 C74VHC14 74VHCT14 Nexperia Hex inverting Schmitt trigger 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74VHC14D -40 C to +125 C SO14 plastic small outline package 14 leads SOT108-1 body width 3.9 mm 74VHCT14D 74VHC14PW 40- C to +125 C TSSOP14 plastic thin shrink small outline package 14 leads SOT402-1 body width 4.4 mm 74VHCT14PW 74VHC14BQ 40- C to +125 C DHVQFN14 plastic dual in-line compatible thermal enhanced very SOT762-1 thin quad at package no leads 14 terminals body 74VHCT14BQ 2.5 3 0.85 mm 4. Functional diagram 1 2 3 4 1A 1Y 2 1 5 6 2A 2Y 3 4 3A 3Y 5 6 9 8 4A 4Y 9 8 11 10 5A 5Y 11 10 6A 6Y 13 12 12 13 A Y mna025 mna204 001aac497 Fig 1. Logic symbol Fig 2. IEC logic symbol Fig 3. Logic diagram (one Schmitt-trigger) 74VHC VHCT14 1 Nexperia B.V. 2017. All rights reserved Product data sheet Rev. 01 17 August 2009 2 of 16