CBT3306D,118 Nexperia

CBT3306 Dual bus switch Rev. 7 1 May 2012 Product data sheet 1. General description The CBT3306 dual FET bus switch features independent line switches. Each switch is disabled when the associated output enable (nOE) input is HIGH. The CBT3306 is characterized for operation from 40 C to +85 C. 2. Features and benefits 5 switch connection between two ports TTL-compatible input levels Multiple package options Latch-up protection exceeds 100 mA per JESD78B ESD protection: HBM JESD22-A114F exceeds 2000 V CDM JESD22-C101D exceeds 1000 V 3. Ordering information Table 1. Ordering information Type number Package Name Description Version CBT3306D SO8 plastic small outline package 8 leads body width 3.9 mm SOT96-1 CBT3306PW TSSOP8 plastic thin shrink small outline package 8 leads SOT530-1 body width 4.4 mm CBT3306GT XSON8 plastic extremely thin small outline package no leads 8 terminals SOT833-1 body 1 1.95 0.5 mm CBT3306GM XQFN8 plastic, extremely thin quad flat package no leads 8 terminals SOT902-2 body 1.6 1.6 0.5 mm 4. Marking Table 2. Marking codes Type number Marking code CBT3306D CBT3306 CBT3306PW 3306 CBT3306GT F06 CBT3306GM F06CBT3306 NXP Semiconductors Dual bus switch 5. Functional diagram 2 3 1A 1B 1 1OE 5 6 2A 2B 7 2OE 002aab985 Fig 1. Logic diagram 6. Pinning information 6.1 Pinning CBT3306 CBT3306 1OE 1 8 V CC 1OE 1 8 V CC 1A 2 7 2OE 1A 2 7 2OE 1B 3 6 2B 1B 3 6 2B GND 4 5 2A GND 4 5 2A 001aak303 001aak304 Fig 2. Pin configuration for SO8 (SOT96-1) Fig 3. Pin configuration for TSSOP8 (SOT530-1) CBT3306 terminal 1 CBT3306 index area 1OE18 V 1OE 1 CC 7 2OE 1A27 2OE 1A 2 6 2B 1B36 2B 1B 3 5 2A GND45 2A 001aal338 001aal337 Transparent top view Transparent top view Fig 4. Pin configuration SOT833-1 (XSON8) Fig 5. Pin configuration SOT902-2 (XQFN8) CBT3306 All information provided in this document is subject to legal disclaimers. NXP B.V. 2012. All rights reserved. Product data sheet Rev. 7 1 May 2012 2 of 14 GND 4 8 V CC