HEF4015BT,653 Nexperia

HEF4015B Dual 4-bit static shift register Rev. 10 26 November 2021 Product data sheet 1. General description The HEF4015B is a dual edge-triggered 4-bit static shift register (serial-to-parallel converter). Each shift register has a serial data input (nD), a clock input (nCP), four fully buffered parallel outputs (Q0 to Q3) and an overriding asynchronous master reset input (nMR). Information present on nD is shifted to the first register position, and all the data in the register is shifted one position to the right on the LOW-to-HIGH transition of nCP. A HIGH on nMR clears the register and forces Q0 to Q3 to LOW, independent of nCP and nD. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of V . DD 2. Features and benefits Wide supply voltage range from 3.0 V to 15.0 V CMOS low power dissipation High noise immunity Tolerant of slow clock rise and fall times Fully static operation 5 V, 10 V, and 15 V parametric ratings Standardized symmetrical output characteristics Complies with JEDEC standard JESD 13-B ESD protection: HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-B exceeds 200 V Specified from -40 C to +85 C 3. Applications Serial-to-parallel converter Buffer stores General purpose register 4. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version HEF4015BT -40 C to +85 C SO16 plastic small outline package 16 leads SOT109-1 body width 3.9 mmNexperia HEF4015B Dual 4-bit static shift register 5. Functional diagram 1Q0 5 7 1D 1Q1 4 SHIFT REGISTER 1Q2 3 4 BITS 9 1CP 1Q3 10 6 1MR 2Q0 13 15 2D 2Q1 12 SHIFT REGISTER 2Q2 11 4 BITS 1 2CP 2Q3 2 14 2MR 001aae560 Fig. 1. Functional diagram Q0 Q1 Q2 Q3 D D Q D Q D Q D Q FF 1 FF 2 FF 3 FF 4 CP CP CP CP CD CD CD CD CP MR 001aae562 Fig. 2. Logic diagram for one register 6. Pinning information 6.1. Pinning HEF4015B 2CP 1 16 V DD 2 15 2Q3 2D 1Q2 3 14 2MR 1Q1 4 13 2Q0 1Q0 5 12 2Q1 1MR 6 11 2Q2 7 10 1D 1Q3 V 8 9 1CP SS 001aae561 Fig. 3. Pin configuration for SOT109-1 (SO16) HEF4015B All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2021. All rights reserved Product data sheet Rev. 10 26 November 2021 2 / 11