HEF4021BT,652 Nexperia

HEF4021B 8-bit static shift register Rev. 11 1 December 2021 Product data sheet 1. General description The HEF4021B is an 8-bit static shift register (parallel-to-serial converter) with a synchronous serial data input (DS), a clock input (CP), an asynchronous active HIGH parallel load input (PL), eight asynchronous parallel data inputs (D0 to D7) and buffered parallel outputs from the last three stages (Q5 to Q7). Each register stage is a D-type master-slave flip-flop with a set direct (SD) and clear direct (CD) input. Information on D0 to D7 is asynchronously loaded into the register while PL is HIGH, independent of CP and DS. When PL is LOW, data on DS is shifted into the first register position and all the data in the register is shifted one position to the right on the LOW-to-HIGH transition of CP. Schmitt trigger action makes the clock input highly tolerant of slower rise and fall times. The device operates over a recommended V power supply range of 3 V to 15 V referenced to DD V (usually ground). Unused inputs must be connected to V , V , or another input. SS DD SS 2. Features and benefits Wide supply voltage range from 3.0 V to 15.0 V CMOS low power dissipation High noise immunity Tolerant of slower rise and fall times Fully static operation 5 V, 10 V, and 15 V parametric ratings Standardized symmetrical output characteristics Complies with JEDEC standard JESD 13-B ESD protection: HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-B exceeds 200 V Specified from -40 C to +85 C and from -40 C to +125 C 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version HEF4021BT -40 C to +125 C SO16 plastic small outline package 16 leads SOT109-1 body width 3.9 mm HEF4021BTT -40 C to +125 C TSSOP16 plastic thin shrink small outline package 16 leads SOT403-1 body width 4.4 mmNexperia HEF4021B 8-bit static shift register 4. Functional diagram 7 6 5 4 13 14 15 1 D0 D1 D2 D3 D4 D5 D6 D7 9 PL SD/CD 11 DS D SHIFT REGISTER 10 CP 8-BITS CP Q5 Q6 Q7 2 12 3 001aae608 Fig. 1. Functional diagram D0 D5 D6 D7 SD SD SD SD DS D O D O D O D O CP CP CP CP FF 1 FF 6 FF 7 FF 8 CD CD CD CD PL CP Q5 Q6 Q7 001aae610 Fig. 2. Logic diagram HEF4021B All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2021. All rights reserved Product data sheet Rev. 11 1 December 2021 2 / 14