HEF4028BT,652 Nexperia

HEF4028B BCD to decimal decoder Rev. 10 7 December 2021 Product data sheet 1. General description The HEF4028B is a 4-bit BCD to 1-of-10 decoder. A 1-2-4-8 BCD code applied to inputs A0 to A3 causes the selected output to be HIGH, the other nine will be LOW. To use as a 1-of-8 decoder with enable, 3-bit octal inputs are applied to inputs A0 , A1 and A2 selecting an output Y0 to Y7 . Input A3 then becomes an active LOW enable, forcing the selected output LOW when A3 is HIGH. The device may also be used as an 8-output (Y0 to Y7) demultiplexer with A0 to A2 as address inputs and A3 as an active LOW data input. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of V . DD 2. Features and benefits Wide supply voltage range from 3.0 V to 15.0 V CMOS low power dissipation High noise immunity Fully static operation 5 V, 10 V, and 15 V parametric ratings Standardized symmetrical output characteristics Complies with JEDEC standard JESD 13-B ESD protection: HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-B exceeds 200 V Specified from -40 C to +85 C 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version HEF4028BT -40 C to +85 C SO16 plastic small outline package 16 leads SOT109-1 body width 3.9 mm 4. Functional diagram A0 A1 A2 A3 10 13 12 11 DECODER 3 14 2 15 1 6 7 4 9 5 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 001aae598 Fig. 1. Functional diagramNexperia HEF4028B BCD to decimal decoder Y0 Y1 A0 Y2 Y3 A1 Y4 Y5 A2 Y6 Y7 A3 Y8 Y9 001aae600 Fig. 2. Logic diagram 5. Pinning information 5.1. Pinning HEF4028B Y4 1 16 V DD Y2 2 15 Y3 Y0 3 14 Y1 Y7 4 13 A1 Y9 5 12 A2 Y5 6 11 A3 Y6 7 10 A0 V 8 9 Y8 SS 001aae599 Fig. 3. Pin configuration SOT109-1 (SO16) HEF4028B All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2021. All rights reserved Product data sheet Rev. 10 7 December 2021 2 / 10