PUMD12 Nexperia

PEMD12 PUMD12 NPN/PNP resistor-equipped transistors R1 = 47 k , R2 = 47 k Rev. 4 21 November 2011 Product data sheet 1. Product profile 1.1 General description NPN/PNP double Resistor-Equipped Transistors (RET) in Surface-Mounted Device (SMD) plastic packages. Table 1. Product overview Type number Package PNP/PNP NPN/NPN Package complement complement configuration NXP JEITA PEMD12 SOT666 - PEMB2 PEMH2 ultra small and flat lead PUMD12 SOT363 SC-88 PUMB2 PUMH2 very small 1.2 Features and benefits 100 mA output current capability Reduces component count Built-in bias resistors Reduces pick and place costs Simplifies circuit design AEC-Q101 qualified 1.3 Applications Low current peripheral driver Control of IC inputs Replaces general-purpose transistors in digital applications 1.4 Quick reference data Table 2. Quick reference data Symbol Parameter Conditions Min Typ Max Unit Per transistor for the PNP transistor (TR2) with negative polarity V collector-emitter voltage open base - - 50 V CEO I output current - - 100 mA O R1 bias resistor 1 (input) 33 47 61 k R2/R1 bias resistor ratio 0.8 1 1.2PEMD12 PUMD12 NXP Semiconductors NPN/PNP resistor-equipped transistors R1 = 47 k , R2 = 47 k 2. Pinning information Table 3. Pinning Pin Description Simplified outline Graphic symbol 1 GND (emitter) TR1 65 4 6 5 4 2 input (base) TR1 3 output (collector) TR2 R1 R2 4 GND (emitter) TR2 TR2 5 input (base) TR2 TR1 1 2 3 6 output (collector) TR1 R2 R1 001aab555 1 23 006aaa143 3. Ordering information Table 4. Ordering information Type number Package Name Description Version PEMD12 - plastic surface-mounted package 6 leads SOT666 PUMD12 SC-88 plastic surface-mounted package 6 leads SOT363 4. Marking Table 5. Marking codes 1 Type number Marking code PEMD12 D2 PUMD12 D*1 1 * = placeholder for manufacturing site code PEMD12 PUMD12 All information provided in this document is subject to legal disclaimers. NXP B.V. 2011. All rights reserved. Product data sheet Rev. 4 21 November 2011 2 of 16