NJM324CG-TE2 Nisshinbo

NJM324C/NJM324CA Low power quad operational amplifiers Features Wide gain bandwidth:1.3MHz typ. Input common-mode voltage range includes ground Large voltage gain:100dB typ. Very low supply current per amplifier:300uA typ. Low input bias current: 20nA typ. Low input offset current: 2nA typ. NJM324CG Wide power supply range: NJM324CAG ( SOP14 ) - Single supply: +3V to +30V - Dual supplies: 1.5V to 15V Internal ESD protection: Human body model (HBM) 2000V typ. Input Offset Voltage Grade NJM324C( Normal-Grade ) NJM324CA( A Grade ) NJM324CV NJM324CAV 7mV max. at Ta=25 2.5mV max. at Ta=25 (SSOP14) 9mV max. at Ta=0 to 70 4mV max. at Ta=0 to 70 Description The NJM324C / NJM324CA consist of four independent, high gain, internally frequency-compensated operational amplifiers. They operate from a single power supply over a wide range of voltages. Operation from split power supplies is also possible and the low power supply current drain is independent of the magnitude of the power supply voltage. 1. Pin and schematic diagram Figure 1. Pin connections (top view) Output 1 1 Output 4 14 4 1 Inverting Input 1 2 13 Inverting Input 4 Non-inverting Input 1 3 12 Non-inverting Input 4 - + V 4 11 V CC CC 10 Non-inverting Input 2 Non-inverting Input 3 5 Inverting Input 2 9 Inverting Input 3 6 3 2 Output 2 Output 3 7 8 ver.09 - 1 - NJM324C/NJM324CA Figure 2. Schematic diagram (1/4 NJM324C / NJM324CA) + Vcc V CC 6A 4A 100A Q5 Q6 C C Q7 Q3 Q2 Inverting inverting R SC Output Q1 Q4 Output Input Input Q11 Non-Inverting Q13 non-inverting Q12 Input Input Q10 Q8 Q9 50A - GND Vcc 2 Absolute maximum ratings Table1. Absolute maximum ratings (Tamb=25C) Symbol Parameter Value Unit + - VCC Supply voltage (VCC - VCC) 32 V (1) - - V Input voltage Vcc -0.3 to Vcc +32 V IN - + V Output Terminal Input Voltage Vcc -0.3 to Vcc +0.3 V o V Differential input voltage 32 V ID (2) 5mA in DC or 50mA in AC (duty cycle = 10%, T=1s) Input current :Vin driven negative I (3) mA IN Input current :Vin driven positive above AMR value 0.4 T Storage temperature range -65 to +150 C stg T Maximum junction temperature 150 C j (5) (6) SOP14 : 880 1200 P Power Dissipation mW D (5) (6) SSOP14 : 510 640 (5) (6) SOP14 : 140 100 (4) ja Thermal resistance junction to ambient (5) (6) C /W SSOP14 : 245 195 (5 ) (6) (4) SOP14 : 40 35 jt Thermal resistance junction to top surface of IC package (5 ) (6) C /W SSOP14 : 49 47 + 1. Input voltage is the voltage should be allowed to apply to the input terminal independent of the magnitude of V CC 2. This input current only exists when the voltage at any of the input leads is driven negative. It is due to the collector-vase junction of the input PNP transistor becoming forward-biased and thereby acting as input diode clamp. In addition to this diode action, there is NPN parasitic action on the IC chip. This transistor action can cause the output voltages of the Op-amps to go to the V voltage level (or to ground for a large overdrive) for the time during CC which an input is driven negative. 3. The junction base/substrate of the input PNP transistor polarized in reverse must be protected by a resistor in series with the inputs to limit the input current to 400uA max (R= (Vin-32V)/400uA). 4. Short-circuit can cause excessive heating and destructive dissipation. Values are typical. 5. EIA/JEDEC STANDARD Test board (76.2 x 114.3 x 1.6mm, 2layers, FR-4) mounting 6. EIA/JEDEC STANDARD Test board (76.2 x 114.3 x 1.6mm, 4layers, FR-4) mounting ver.09 - 2 -