NJU6366 Series Small Sized Quartz Crystal Oscillator GENERAL DESCRIPTION PACKAGE OUTLINE The NJU6366 series is a C-MOS fundamental quartz crystal oscillator that consists of an oscillation amplifier, 3-stage divider and 3-state output buffer. The 3-stage divider generates only one frequency selected of f ,f /2,f /4 and f /8 by internal circuits is output. NJU6366XC-C NJU6366XF1 0 0 0 0 The oscillation amplifier is realized very low stand-by current using NAND circuit. The 3-state output buffer is C-MOS compatible Furthermore, the package is small-sized SOT-23-6-1. FEATURES PAD LOCATION/PIN CONFIGURATION Operating Voltage 2.0 to 5.5V Thin-Chip Maximum Oscillation Frequency 50MHz F OUT XT Low Operating Current V High Fan-out I /I =4mA 2.5V OH OL DD 3-Stage Divider One of f ,f /2,f /4 and f /8 0 0 0 0 V SS CONT Oscillation Stop and Output Stand-by Function XT 3-State Output Buffer Oscillation Capacitors Cg and Cg on-chip SOT-23-6-1 Package Outline Thin-Chip/SOT-23-6-1 1 6 F V OUT SS C-MOS Technology 2 5 V XT DD 3 4 XT CONT LINE-UP TABLE COORDINATES Internal Connect Pad Name X Y Type No. F Cg/Cd OUT Connect Non Connect F -207 247 OUT A f A Line B,C,D Line 23/23pF 0 V -207 -247 SS B f /2 B Line A,C,D Line 23/23pF 0 NJU6366 XT 33 -247 23/23pF C f /4 C Line A,B,D Line 0 207 -247 D f /8 D Line A,B,C Line 23/23pF CONT 0 V 207 -17 DD 207 172 XT Starting Point:Chip Center Unit um Chip Size:0.67x0.75mm Thin-Chip Thickness(-C):260 20um Pad Size:90x90um Die Substrate: V Level DD BLOCK DIAGRAM XT V V DD SS Rf XT 1/2 1/2 1/2 Cg Cd 3-STATE F OUT BUFFER A B C D CONT 2016/08/22 ( 1 / 6 ) NJU6366 Series TERMINAL DESCRIPTION SYMBOL FUNCTION Oscillation and 3-state Output Buffer Control F CONT OUT Output either one frequency selected of f , 0 CONT H or OPEN f /2,f /4 and f /8 Note1) 0 0 0 L Oscillation Stop and High impedance Output XT Quartz Crystal Connecting Terminals XT V V =0V SS SS F Frequency Output OUT V V =2.5V/3.0V/5.0V DD DD Note1) Refer to the line-up table. ABSOLUTE MAXIMUM RATINGS (Ta=25C) PARAMETER SYMBOL RATING UNIT Supply Voltage V -0.5 to +7.0 V DD Input Voltage V V -0.5 to V +0.5 V IN SS DD Output Voltage V -0.5 to V +0.5 V O DD Input Current I 10 mA IN Output Current I 25 mA O Power Dissipation P 200(SOT-23-6-1) mW D Note4) Operating Temperature Range Topr -40 to +85 C Storage Temperature Range Tstg -55 to +125 C Note2) If the supply voltage(V ) is less than 7.0V, the input voltage must not over the V level though 7.0V is DD DD limit specified. Note3) Decupling capacitor should be connected between V and V due to the stabilized operation for the DD SS circuit. Note4) The power dissipation is the maximum value at only the package. 2016/08/22 ( 2 / 6 )