NTE4001BT NTE

NTE4001B & NTE4001BT Integrated Circuit CMOS, Quad 2Input NOR Gate Description: The NTE4001B (14 Lead DIP) and NTE4001BT (SOIC 14) are quad 2 input NOR gate devices constructed with P Channel and N Channel enhancement mode devices in a single monolithic structure. These complementary MOS logic gates find primary use where low power dissipation and/or high noise immunity is desired. Features: Supply Voltage Range: 3Vdc to 18Vdc All Outputs Buffered Capable of Driving Two Low Power TTL Loads or One Low Power Schottky TTL Load Over the Rated Temperature Range Double Diode Protection on All Inputs Absolute Maximum Ratings: (Voltages referenced to V , Note 1) SS DC Supply Voltage, V .................................................. 0.5 to +18.0V DD Input Voltage (DC or Transient), V .................................... 0.5 to V to +0.5V in DD Output Voltage (DC or Transient), V ................................. 0.5 to V to +0.5V out DD Input Current (DC or Transient, Per Pin), I ......................................... 10mA in Output Current (DC or Transient, Per Pin), I ...................................... 10mA out Power Dissipation (Per Package), P ............................................. 500mW D Temperature Derating (from +65 to +125C) ............................. 7.0mW/C Storage Temperature, T ................................................. 65 to +150C stg Lead Temperature (During Soldering, 8sec max), T ................................. +260C L Note 1. Maximum Ratings are those values beyond which damage to the device may occur.Electrical Characteristics: (Voltages referenced to V , Note 2) SS 55 C +25 C +125 C V DD Min Max Min Typ Max Min Max Parameter Symbol Vdc Unit Output Voltage 0 Level V 5.0 0.05 0 0.05 0.05 Vdc OL V = V or 0 10 0.05 0 0.05 0.05 Vdc in DD 15 0.05 0 0.05 0.05 Vdc 1 Level V 5.0 4.95 4.95 5.0 4.95 Vdc OH V = 0 or V 10 9.95 9.95 10 9.95 Vdc in DD 15 14.95 14.95 15 14.95 Vdc Input Voltage 0 Level V IL (V = 4.5 or 0.5Vdc) 5.0 1.5 2.25 1.5 1.5 Vdc O (V = 9.0 or 1.0Vdc) 10 3.0 4.50 3.0 3.0 Vdc O (V = 13.5 or 1.5Vdc) 15 4.0 6.75 4.0 4.0 Vdc O 1 Level V IH (V = 0.5 or 4.5Vdc) 5.0 3.5 3.5 2.75 3.5 Vdc O (V = 1.0 or 9.0Vdc) 10 7.0 7.0 5.50 7.0 Vdc O (V = 1.5 or 13.5Vdc) 15 11.0 11.0 8.25 11.0 Vdc O Output Drive Current Source I OH (V = 2.5Vdc) 5.0 3.0 2.4 4.2 1.7 mAdc OH (V = 4.6Vdc) 5.0 0.64 0.51 0.88 0.36 mAdc OH (V = 9.5Vdc) 10 1.6 1.3 2.25 0.9 mAdc OH (V = 13.5Vdc) 15 4.2 3.4 8.8 2.4 mAdc OH Sink I OL (V = 0.4Vdc) 5.0 0.64 0.51 0.88 0.36 mAdc OL (V = 0.5Vdc) 10 1.6 1.3 2.25 0.9 mAdc OL (V = 1.5Vdc) 15 4.2 3.4 8.8 2.4 mAdc OL Input Current I 15 0.1 0.00001 0.1 0.1 Adc in Input Capacitance (V = 0) C 5.0 7.5 pF IN in I 5.0 0.25 0.0005 0.25 7.5 Adc Quiescent Current DD (Per Package) 10 0.5 0.0010 0.5 15 Adc 15 1.0 0.0015 1.0 30 Adc I 5.0 I = (0.3A/kHz) f + I /N Adc Total Supply Current T T DD (Dynamic plus Quiescent, 10 I = (0.6A/kHz) f + I /N Adc T DD = 50pF, Per Gate, C L Note 3, Note 4) 15 I = (0.8A/kHz) f + I /N Adc T DD Note 2. Data labeled Typ is not to be used for design purposes but is intended as an indication of the devices potential performance. Note 3. The formulas given are for the typical characteristics only at +25C. Note 4. To calculate total supply current at loads other than 50pF: I (C ) = I (50pF) + (C 50) V T L T L fk where: I is in H (per package), C in pF, V = (V V ) in volts, f in kHz is input frequency, T L DD SS and k = 0.001 x the number of exercised gates per package.