74AUP2G132GM,125 NXP

74AUP2G132 Low-power dual 2-input NAND Schmitt trigger Rev. 7 8 February 2013 Product data sheet 1. General description The 74AUP2G132 provides the dual 2-input NAND Schmitt trigger function which accepts standard input signals. They can transform slowly changing input signals into sharply defined, jitter-free output signals. This device ensures a very low static and dynamic power consumption across the entire V range from 0.8 V to 3.6 V. CC This device is fully specified for partial power-down applications using I . The I OFF OFF circuitry disables the output, preventing a damaging backflow current through the device when it is powered down. The inputs switch at different points for positive and negative-going signals. The difference between the positive voltage V and the negative voltage V is defined as the input T+ T hysteresis voltage V . H 2. Features and benefits Wide supply voltage range from 0.8 V to 3.6 V High noise immunity ESD protection: HBM JESD22-A114F Class 3A exceeds 5000 V MM JESD22-A115-A exceeds 200 V CDM JESD22-C101E exceeds 1000 V Low static power consumption I = 0.9 A (maximum) CC Latch-up performance exceeds 100 mA per JESD 78 Class II Inputs accept voltages up to 3.6 V Low noise overshoot and undershoot < 10 % of V CC I circuitry provides partial Power-down mode operation OFF Multiple package options Specified from 40 C to +85 C and 40 C to +125 C 3. Applications Wave and pulse shaper Astable multivibrator Monostable multivibrator74AUP2G132 NXP Semiconductors Low-power dual 2-input NAND Schmitt trigger 4. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74AUP2G132DC 40 C to +125 C VSSOP8 plastic very thin shrink small outline package 8 leads SOT765-1 body width 2.3 mm 74AUP2G132GT 40 C to +125 C XSON8 plastic extremely thin small outline package no leads SOT833-1 8 terminals body 1 1.95 0.5 mm 74AUP2G132GF 40 C to +125 C XSON8 extremely thin small outline package no leads SOT1089 8 terminals body 1.35 1 0.5 mm 74AUP2G132GD 40 Cto +125 C XSON8 plastic extremely thin small outline package no leads SOT996-2 8 terminals body 3 2 0.5 mm 74AUP2G132GM 40 C to +125 C XQFN8 plastic, extremely thin quad flat package no leads SOT902-2 8 terminals body 1.6 1.6 0.5 mm 74AUP2G132GN 40 C to +125 C XSON8 extremely thin small outline package no leads SOT1116 8 terminals body 1.2 1.0 0.35 mm 74AUP2G132GS 40 C to +125 C XSON8 extremely thin small outline package no leads SOT1203 8 terminals body 1.35 1.0 0.35 mm 5. Marking Table 2. Marking codes 1 Type number Marking code 74AUP2G132DC aE2 74AUP2G132GT aE2 74AUP2G132GF aE 74AUP2G132GD aE2 74AUP2G132GM aE2 74AUP2G132GN aE 74AUP2G132GS aE 1 The pin 1 indicator is located on the lower left corner of the device, below the marking code. 6. Functional diagram 1A 1Y & 1B 2A A & 2Y Y 2B B 001aah880 001aah881 001aac532 Fig 1. Logic symbol Fig 2. IEC logic symbol Fig 3. Logic diagram (one gate) 74AUP2G132 All information provided in this document is subject to legal disclaimers. NXP B.V. 2013. All rights reserved. Product data sheet Rev. 7 8 February 2013 2 of 23