74HC165D-Q100,118 NXP

74HC165-Q100 74HCT165-Q100 8-bit parallel-in/serial out shift register Rev. 1 17 July 2012 Product data sheet 1. General description The 74HC165-Q100 74HCT165-Q100 are high-speed Si-gate CMOS devices that comply with JEDEC standard no. 7A. They are pin compatible with Low-power Schottky TTL (LSTTL). The 74HC165-Q100 74HCT165-Q100 are 8-bit parallel-load or serial-in shift registers with complementary serial outputs (Q7 and Q7) available from the last stage. When the parallel load (PL) input is LOW, parallel data from the D0 to D7 inputs are loaded into the register asynchronously. When PL is HIGH, data enters the register serially at the DS input and shifts one place to the right (Q0 Q1 Q2, etc.) with each positive-going clock transition. This feature allows parallel-to-serial converter expansion by tying the Q7 output to the DS input of the succeeding stage. The clock input is a gated-OR structure which allows one input to be used as an active LOW clock enable (CE) input. The pin assignment for the CP and CE inputs is arbitrary and can be reversed for layout convenience. The LOW-to-HIGH transition of input CE should only take place while CP HIGH for predictable operation. Either the CP or the CE should be HIGH before the LOW-to-HIGH transition of PL to prevent shifting the data when PL is activated. This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications. 2. Features and benefits Automotive product qualification in accordance with AEC-Q100 (Grade 1) Specified from 40 C to +85 C and from 40 C to +125 C Asynchronous 8-bit parallel load Synchronous serial input Complies with JEDEC standard no. 7A ESD protection: MIL-STD-883, method 3015 exceeds 2000 V HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 ) Multiple package options 3. Applications Parallel-to-serial data conversion74HC165-Q100 74HCT165-Q100 Nexperia 8-bit parallel-in/serial out shift register 4. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74HC165D-Q100 40 C to +125 C SO16 plastic small outline package 16 leads body width SOT109-1 3.9 mm 74HCT165D-Q100 74HC165PW-Q100 40 C to +125 C TSSOP16 plastic thin shrink small outline package 16 leads SOT403-1 body width 4.4 mm 74HCT165PW-Q100 74HC165BQ-Q100 40 C to +125 C DHVQFN16 plastic dual in-line compatible thermal enhanced SOT763-1 very thin quad flat package no leads 16 terminals 74HCT165BQ-Q100 body 2.5 3.5 0.85 mm 5. Functional diagram SRG8 1 C2 LOAD G1 SHIFT 15 1 10 C3/ 1 2 DS 11 D0 10 3D 12 D1 11 2D 13 D2 12 14 2D D3 13 3 D4 14 4 D5 3 5 9 D6 Q7 4 6 7 D7 Q7 1 5 PL 9 CP CE 6 7 2 15 mna985 mna986 Fig 1. Logic symbol Fig 2. IEC logic symbol 74HC HCT165 Q100 All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2017. All rights reserved Product data sheet Rev. 1 17 July 2012 2 of 21