74HC2G86GD,125 NXP

74HC2G86 74HCT2G86 Dual 2-input EXCLUSIVE-OR gate Rev. 5 18 December 2018 Product data sheet 1. General description The 74HC2G86 74HCT2G86 is a dual 2-input EXCLUSIVE-OR gate. Inputs include clamp diodes that enable the use of current limiting resistors to interface inputs to voltages in excess of V . CC 2. Features and benefits Wide supply voltage range from 2.0 V to 6.0 V Input levels: For 74HC2G86: CMOS level For 74HCT2G86: TTL level Symmetrical output impedance High noise immunity Low power dissipation Balanced propagation delays ESD protection: HBM JESD22-A114E exceeds 2000 V MM JESD22-A115-A exceeds 200 V Specified from -40 C to +85 C and -40 C to +125 C 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74HC2G86DP -40 C to +125 C TSSOP8 plastic thin shrink small outline package 8 leads SOT505-2 body width 3 mm lead length 0.5 mm 74HC2G86DC -40 C to +125 C VSSOP8 plastic very thin shrink small outline package SOT765-1 8 leads body width 2.3 mm 74HCT2G86DC 4. Marking Table 2. Marking code Type number Marking code 1 74HC2G86DP H86 74HC2G86DC H86 74HCT2G86DC T86 1 The pin 1 indicator is located on the lower left corner of the device, below the marking code.Nexperia 74HC2G86 74HCT2G86 Dual 2-input EXCLUSIVE-OR gate 5. Functional diagram = 1 1A 1Y 1B 2A 2Y = 1 2B 001aah760 001aah761 Fig. 1. Logic symbol Fig. 2. IEC logic symbol B Y A mna040 Fig. 3. Logic diagram (one gate) 6. Pinning information 6.1. Pinning 74HC2G86 74HCT2G86 1A 1 8 V CC 1B 2 7 1Y 2Y 3 6 2B GND 4 5 2A 001aak026 Fig. 4. Pin configuration SOT505-2 (TSSOP8) and SOT765-1 (VSSOP8) 6.2. Pin description Table 3. Pin description Symbol Pin Description 1A, 2A 1, 5 data input 1B, 2B 2, 6 data input GND 4 ground (0 V) 1Y, 2Y 7, 3 data output V 8 supply voltage CC 74HC HCT2G86 All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2018. All rights reserved Product data sheet Rev. 5 18 December 2018 2 / 11