INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT4059
Programmable divide-by-n counter
1998 Jul 08
Product specication
Supersedes data of September 1993
File under Integrated Circuits, IC06Philips Semiconductors Product specication
Programmable divide-by-n counter 74HC/HCT4059
FEATURES In the divide-by-n mode, a clock cycle wide pulse is
generated with a frequency rate equal to the input
Synchronous programmable divide-by-n counter
frequency divided by n.
Presettable down counter
The function of the mode select and JAM inputs are
Fully static operation
illustrated in the following examples. In the divide-by-2
Mode select control of initial decade counting function
mode, only one flip-flop is needed in the first counting
(divide-by-10, 8, 5, 4 and 2) section. Therefore the last (5th) counting section has three
flip-flops that can be preset to a maximum count of seven
Master preset initialization
with a place value of thousands. This counting mode is
Latchable output
selected when K to K are set HIGH. In this case input J
a c 1
Easily cascadable with other counters
is used to preset the first counting section and J to J are
2 4
used to preset the last (5th) counting section.
Four operating modes:
timer
If the divide-by-10 mode is desired for the first section, K
a
divider-by-n
and K are set HIGH and K is set LOW. The JAM inputs
b c
divide-by-10 000
J to J are used to preset the first counting section (there
1 4
master preset
is no last counting section). The intermediate counting
Output capability: standard section consists of three cascaded BCD decade
(divide-by-10) counters, presettable by means of the JAM
I category: MSI
CC
inputs J to J .
5 16
The preset of the counter to a desired divide-by-n is
GENERAL DESCRIPTION
achieved as follows:
The 74HC/HCT4059 are high-speed Si-gate CMOS
(1)
n = (MODE ) (1 000 x decade 5 preset
devices and are pin compatible with the 4059 of the
+ 100 x decade 4 preset
4000B series. They are specified in compliance with
+ 10 x decade 3 preset
JEDEC standard no. 7A.
+ 1 x decade 2 preset)
The 74HC/HCT4059 are divide-by-n counters which can
+ decade 1 preset
be programmed to divide an input frequency by any
To calculate preset values for any n count, divide the n
number (n) from 3 to 15 999. There are four operating
count by the selected mode. The resultant is the
modes, timer, divide-by-n, divide-by-10 000 and master
corresponding preset value of the 5th to the 2nd decade
preset, which are defined by the mode select inputs (K to
a
with the remainder being equal to the 1st decade value;
K ) and the latch enable input (LE) as shown in the
c
preset value = n/mode.
Function table.
If n = 8 479, and the selected mode = 5, the preset
The complete counter consists of a first counting stage, an
value = 8 479/5 = 1 695 with a remainder of 4, thus the
intermediate counting stage and a fifth counting stage. The
JAM inputs must be set as shown in Table 1.
first counter stage consists of four independent flip-flops.
Depending on the divide-by-mode, at least one flip-flop is
To verify the results, use the given equation:
placed at the input of the intermediate stage (the remaining
n = 5 (1 000 1 + 100 6 + 10 9 + 1 5) + 4
flip-flops are placed at the fifth stage with a place value of
thousands). The intermediate stage consists of three
n = 8 479.
cascaded decade counters, each containing four flip-flops.
If n = 12 382 and the selected mode = 8, the preset
All flip-flops can be preset to a desired state by means of
value = 12 382/8 = 1 547 with a remainder of 6, thus the
the JAM inputs (J to J ), during which the clock input
1 16
JAM inputs must be set as shown in Table 2.
(CP) will cause all stages to count from n to zero. The
To verify:
zero-detect circuit will then cause all stages to return to the
JAM count, during which an output pulse is generated. In
n = 8 (1 000 1 + 100 5 + 10 4 + 1 7) + 6
the timer mode, after an output pulse is generated, the
n = 12 382.
output pulse remains HIGH until the latch input (LE) goes
LOW. The counter will advance, even if LE is HIGH and
(1) MODE = first counting section divider
the output is latched in the HIGH state.
(10, 8, 5, 4 or 2).
1998 Jul 08 2