74HC564N,652 NXP

74HC564 Octal D-type ip-op positive-edge trigger 3-state inverting Rev. 03 11 November 2004 Product data sheet 1. General description The 74HC564 is a high-speed Si-gate CMOS device and is pin compatible with low-power Schottky TTL (LSTTL). The 74HC564 is specied in compliance with JEDEC standard no. 7A. The 74HC564 is a octal D-type ip-op featuring separate D-type inputs for each ip-op and inverting 3-state outputs for bus oriented applications. A clock (CP) and an output enable (OE) input are common to all ip-ops. The 8 ip-ops will store the state of their individual D-inputs that meet the set-up and hold times requirements on the LOW-to-HIGH CP transition. When OE is LOW, the contents of the 8 ip-ops are available at the outputs. When OE is HIGH, the outputs go to the high-impedance OFF-state. Operation of the OE input does not affect the state of the ip-ops. The 74HC564 is functionally identical to the 74HC574 but has inverting outputs. The 74HC564 is functionally identical to the 74HC534, but has a different pinning. 2. Features 3-state inverting outputs for bus oriented applications 8-bit positive-edge triggered register Common 3-state output enable input Independent register and 3-state buffer operation Low-power dissipation Complies with JEDEC standard no. 7A ESD protection: HBM EIA/JESD22-A114-B exceeds 2000 V MM EIA/JESD22-A115-A exceeds 200 V. Multiple package options Specied from - 40 Cto+80 C and from - 40 C to +125 C.74HC564 Philips Semiconductors Octal D-type ip-op positive-edge trigger 3-state inverting 3. Quick reference data Table 1: Quick reference data GND = 0 V T =25 C t =t = 6 ns. amb r f Symbol Parameter Conditions Min Typ Max Unit t , t propagation delay CP C = 15 pF -15 - ns PHL PLH L to Qn V =5 V CC f maximum clock C = 15 pF - 127 - MHz max L frequency V =5 V CC C input capacitance - 3.5 - pF I 1 C power dissipation V = GND to V -27 - pF PD I CC capacitance per ip-op 1 C is used to determine the dynamic power dissipation (P in W). PD D 2 2 P =C V f N+ (C V f ) where: D PD CC i L CC o f = input frequency in MHz i f = output frequency in MHz o C = output load capacitance in pF L V = supply voltage in V CC N = number of inputs switching 2 (C V f ) = sum of outputs. L CC o 4. Ordering information Table 2: Ordering information Type number Package Temperature range Name Description Version 74HC564N - 40 C to +125 C DIP20 plastic dual in-line package 20 leads (300 mil) SOT146-1 74HC564D - 40 C to +125 C SO20 plastic small outline package 20 leads SOT163-1 body width 7.5 mm 9397 750 13814 Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data sheet Rev. 03 11 November 2004 2 of 18