74HC73N,652 NXP

74HC73 Dual JK flip-flop with reset negative-edge trigger Rev. 5 2 December 2015 Product data sheet 1. General description The 74HC73 is a dual negative edge triggered JK flip-flop with individual J, K, clock (nCP) and reset (nR) inputs and complementary nQ and nQ outputs. The J and K inputs must be stable one set-up time prior to the HIGH-to-LOW clock transition for predictable operation. (nR) is asynchronous, when LOW it overrides the clock and data inputs, forcing the nQ output LOW and the nQ output HIGH. Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of V . CC 2. Features and benefits Low-power dissipation Complies with JEDEC standard no. 7A ESD protection: HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V Multiple package options Specified from 40 Cto+80 C and from 40 Cto+125 C 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74HC73D 40 C to +125 C SO14 plastic small outline package 14 leads body width 3.9 mm SOT108-1 74HC73DB 40 C to +125 C SSOP14 plastic shrink small outline package 14 leads body width SOT337-1 5.3 mm 74HC73PW 40 C to +125 C TSSOP14 plastic thin shrink small outline package 14 leads body SOT402-1 width 4.4 mm74HC73 Nexperia Dual JK flip-flop with reset negative-edge trigger 4. Functional diagram 4 - 4 )) 3 4 . 4 5 4 - 4 )) 3 4 . 4 5 DE D Fig 1. Functional diagram - 4 - 4 - 4 5 3 3 4 . 4 4 5 5 D DE DE D Fig 2. Logic symbol Fig 3. IEC logic symbol 74HC73 All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2017. All rights reserved Product data sheet Rev. 5 2 December 2015 2 of 16 5 5 . & - & &3 & )) . & - 5 . &3 & - 5 . &3 & -