74HC86N NXP

74HC86 74HCT86 Quad 2-input EXCLUSIVE-OR gate Rev. 3 27 August 2012 Product data sheet 1. General description The 74HC86 74HCT86 are high-speed Si-gate CMOS devices that comply with JEDEC standard no. 7A. They are pin compatible with Low-power Schottky TTL (LSTTL). The 74HC86 74HCT86 provides a 2-input EXCLUSIVE-OR function. 2. Features and benefits Input levels: For 74HC86: CMOS level For 74HCT86: TTL level ESD protection: HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V Multiple package options Specified from 40 C to +85 C and from 40 C to +125 C 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74HC86N 40 C to +125 C DIP14 plastic dual in-line package 14 leads (300 mil) SOT27-1 74HCT86N 74HC86D 40 C to +125 C SO14 plastic small outline package 14 leads body width SOT108-1 3.9 mm 74HCT86D 74HC86DB 40 C to +125 C SSOP14 plastic shrink small outline package 14 leads body SOT337-1 width 5.3 mm 74HCT86DB 74HC86PW 40 C to +125 C TSSOP14 plastic thin shrink small outline package 14 leads SOT402-1 body width 4.4 mm 74HCT86PW74HC86 74HCT86 NXP Semiconductors Quad 2-input EXCLUSIVE-OR gate 4. Functional diagram 1 1A 3 1Y 2 1B 4 2A 6 2Y 5 2B 9 3A 8 3Y 10 3B 12 4A 11 4Y 13 4B mna787 Fig 1. Logic symbol 1 =1 3 2 4 =1 6 5 9 =1 8 10 A 12 Y =1 11 13 B mna788 mna786 Fig 2. Logic diagram (one gate) Fig 3. IEC logic symbol 74HC HCT86 All information provided in this document is subject to legal disclaimers. NXP B.V. 2012. All rights reserved. Product data sheet Rev. 3 27 August 2012 2 of 16