74HCT139N NXP

74HC139 74HCT139 Dual 2-to-4 line decoder/demultiplexer Rev. 4 11 December 2015 Product data sheet 1. General description The 74HC139 74HCT139 decodes two binary weighted address inputs (nA0, nA1) to four mutually exclusive outputs (nY0 to nY3). Each decoder features an enable input (nE). When nE is HIGH all outputs are forced HIGH. The enable input can be used as the data input for a 1-to-4 demultiplexer application. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of V . CC 2. Features and benefits Input levels: For 74HC139: CMOS level For 74HCT139: TTL level Demultiplexing capability 2 independent 2-to-4 decoders Multifunction capability Suitable for memory decoding, data routing or code conversion Complies with JEDEC standard no. 7A Active LOW mutually exclusive outputs ESD protection: HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V Multiple package options Specified from 40 Cto+85 C and from 40 Cto+125 C 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74HC139D 40 Cto+125 C SO16 plastic small outline package 16 leads SOT109-1 body width 3.9 mm 74 HCT139D 74HC139DB 40 Cto+125 C SSOP16 plastic shrink small outline package 16 leads SOT338-1 body width 5.3 mm 74HCT139DB 74HC139PW 40 Cto+125 C TSSOP16 plastic thin shrink small outline package SOT403-1 16 leads body width 4.4 mm 74HCT139PW74HC139 74HCT139 Nexperia Dual 2-to-4 line decoder/demultiplexer 4. Functional diagram < < (&2 (5 < < ( < < < < < < (&2 (5 < < < < < < ( DDD DDD Fig 1. Logic symbol Fig 2. Functional diagram < * (1 < * (1 DDD DDD a. b. Fig 3. IEC Logic symbol 74HC HCT139 All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2017. All rights reserved Product data sheet Rev. 4 11 December 2015 2 of 17 ( (